This patch fixes PR target/78862. Add blockage to prevent the
scheduler from reordering a LR save with a subsequent instruction that
changes the CFA register. This trips up the dwarf generating logic.
Bootstrapped and tested on TILEPro/TILE-Gx hardware, also backported
to GCC 6.
* config/tilegx/tilegx.md (tilegx_expand_prologue): Add blockage
after initial stackframe link reg save.
* config/tilepro/tilepro.md (tilepro_expand_prologue): Likewise.
diff --git a/gcc/config/tilegx/tilegx.c b/gcc/config/tilegx/tilegx.c
index b04e708..d8ca14b 100644
--- a/gcc/config/tilegx/tilegx.c
+++ b/gcc/config/tilegx/tilegx.c
@@ -3998,8 +3998,11 @@ tilegx_expand_prologue (void)
/* Save lr first in its special location because code after this
might use the link register as a scratch register. */
if (df_regs_ever_live_p (TILEGX_LINK_REGNUM) || crtl->calls_eh_return)
- FRP (frame_emit_store (TILEGX_LINK_REGNUM, TILEGX_LINK_REGNUM,
- stack_pointer_rtx, stack_pointer_rtx, 0));
+ {
+ FRP (frame_emit_store (TILEGX_LINK_REGNUM, TILEGX_LINK_REGNUM,
+ stack_pointer_rtx, stack_pointer_rtx, 0));
+ emit_insn (gen_blockage ());
+ }
if (total_size == 0)
{
diff --git a/gcc/config/tilepro/tilepro.c b/gcc/config/tilepro/tilepro.c
index b16ad38..aa1bb1c 100644
--- a/gcc/config/tilepro/tilepro.c
+++ b/gcc/config/tilepro/tilepro.c
@@ -3533,8 +3533,11 @@ tilepro_expand_prologue (void)
/* Save lr first in its special location because code after this
might use the link register as a scratch register. */
if (df_regs_ever_live_p (TILEPRO_LINK_REGNUM) || crtl->calls_eh_return)
- FRP (frame_emit_store (TILEPRO_LINK_REGNUM, TILEPRO_LINK_REGNUM,
- stack_pointer_rtx, stack_pointer_rtx, 0));
+ {
+ FRP (frame_emit_store (TILEPRO_LINK_REGNUM, TILEPRO_LINK_REGNUM,
+ stack_pointer_rtx, stack_pointer_rtx, 0));
+ emit_insn (gen_blockage ());
+ }
if (total_size == 0)
{
--
2.7.2