On Sun, Feb 5, 2017 at 8:50 AM, James Greenhalgh <james.greenha...@arm.com> wrote: > On Fri, Feb 03, 2017 at 01:10:36PM -0800, Andrew Pinski wrote: >> Hi, >> It turns out due to a hardware issue, LSE support is turned off. >> This patch updates the thunderx cores to disable LSE and 8.1 where as >> needed. > > With this, do we want to back out the rest of the "variant" support that > you added to the -mcpu=native detection? > > I'd expect this code to now be dead, and posisbly stay dead. As we only added > it for GCC 7 I don't think losing it again would be a big loss. I realise > that makes this patch a bit larger, but it seems like it would lead to a > more maintainable port. Outside of merge conflicts in aarch64-cores.def, I'd > guess a revert would be fairly painless. > > What do you think?
Well for gcc 8, I was going to propose some scheduling changes which need this again. So the question do we want to keep it around still for GCC 7 or not? IIRC the xgene folks was asking for the variant patch too. Thanks, Andrew > > Thanks, > James > >> >> OK? Bootstrapped and tested on aarch64-linux-gnu with no regressions. >> >> Thanks, >> Andrew Pinski >> >> ChangeLog: >> * config/aarch64/aarch64-cores.def (thunderx): Disable LSE. >> (thunderxt88): Likewise. >> (thunderxt81): Disable LSE and change v8.1 to v8. >> (thunderxt83): Likewise. > >> Index: config/aarch64/aarch64-cores.def >> =================================================================== >> --- config/aarch64/aarch64-cores.def (revision 244077) >> +++ config/aarch64/aarch64-cores.def (working copy) >> @@ -60,13 +60,13 @@ AARCH64_CORE("falkor", falkor, c >> AARCH64_CORE("qdf24xx", qdf24xx, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 >> | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, qdf24xx, 0x51, 0xC00, -1) >> >> /* Cavium ('C') cores. */ >> -AARCH64_CORE("thunderx", thunderx, thunderx, 8A, >> AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO | AARCH64_FL_LSE, >> thunderx, 0x43, 0x0a0, -1) >> +AARCH64_CORE("thunderx", thunderx, thunderx, 8A, >> AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx, 0x43, >> 0x0a0, -1) >> /* Do not swap around "thunderxt88p1" and "thunderxt88", >> this order is required to handle variant correctly. */ >> -AARCH64_CORE("thunderxt88p1", thunderxt88p1, thunderx, 8A, >> AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, >> thunderx, 0x43, 0x0a1, 0) >> -AARCH64_CORE("thunderxt88", thunderxt88, thunderx, 8A, >> AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO | AARCH64_FL_LSE, >> thunderx, 0x43, 0x0a1, -1) >> -AARCH64_CORE("thunderxt81", thunderxt81, thunderx, 8_1A, >> AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO | AARCH64_FL_LSE, >> thunderx, 0x43, 0x0a2, -1) >> -AARCH64_CORE("thunderxt83", thunderxt83, thunderx, 8_1A, >> AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO | AARCH64_FL_LSE, >> thunderx, 0x43, 0x0a3, -1) >> +AARCH64_CORE("thunderxt88p1", thunderxt88p1, thunderx, 8A, >> AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx, >> 0x43, 0x0a1, 0) >> +AARCH64_CORE("thunderxt88", thunderxt88, thunderx, 8A, >> AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx, 0x43, >> 0x0a1, -1) >> +AARCH64_CORE("thunderxt81", thunderxt81, thunderx, 8A, >> AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx, 0x43, >> 0x0a2, -1) >> +AARCH64_CORE("thunderxt83", thunderxt83, thunderx, 8A, >> AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx, 0x43, >> 0x0a3, -1) >> >> /* APM ('P') cores. */ >> AARCH64_CORE("xgene1", xgene1, xgene1, 8A, >> AARCH64_FL_FOR_ARCH8, xgene1, 0x50, 0x000, -1) > >