This patch allows lra to reload a lo_sum address. Given a mem with a
lo_sum address as used by ppc32, decompose_mem_address returns an
address_info with *base the lo_sum and *base_term the reg within the
lo_sum. When a lo_sum address isn't valid, we want to first try
reloading the entire lo_sum to a new reg. I first fixed that, then
hit another ICE, this time in gen_int_mode. gen_int_mode was being
called with the mode of the memory access, not the mode of the
address.
Bootstrapped and regression tested powerpc64le-linux and
powerpc64-linux bi-arch. OK to apply?
PR rtl-optimization/79584
* lra-constraints.c (base_to_reg): Reload ad->base, the entire
base, not ad->base_term, the reg within base. Remove assertion
that ad->base == ad->base_term. Replace gen_int_mode using
bogus mode with const0_rtx.
diff --git a/gcc/lra-constraints.c b/gcc/lra-constraints.c
index bd5fbcd..0e98f22 100644
--- a/gcc/lra-constraints.c
+++ b/gcc/lra-constraints.c
@@ -2916,18 +2916,18 @@ base_to_reg (struct address_info *ad)
rtx_insn *insn;
rtx_insn *last_insn = get_last_insn();
- lra_assert (ad->base == ad->base_term && ad->disp == ad->disp_term);
+ lra_assert (ad->disp == ad->disp_term);
cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code,
get_index_code (ad));
- new_reg = lra_create_new_reg (GET_MODE (*ad->base_term), NULL_RTX,
+ new_reg = lra_create_new_reg (GET_MODE (*ad->base), NULL_RTX,
cl, "base");
new_inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), new_reg,
ad->disp_term == NULL
- ? gen_int_mode (0, ad->mode)
+ ? const0_rtx
: *ad->disp_term);
if (!valid_address_p (ad->mode, new_inner, ad->as))
return NULL_RTX;
- insn = emit_insn (gen_rtx_SET (new_reg, *ad->base_term));
+ insn = emit_insn (gen_rtx_SET (new_reg, *ad->base));
code = recog_memoized (insn);
if (code < 0)
{
--
Alan Modra
Australia Development Lab, IBM
