On 04/26/2017 08:29 AM, Peryt, Sebastian wrote:
Hi,
This patch updates x86 family machine constraints section in '16.8.5
Constraints for Particular Machines' section to match the ones in
'config/i386/constraints.md'.
gcc/
* doc/md.texi (Machine Constraints): Update x86 family machine
constraints
section to match 'config/i386/constraints.md'.
Is it ok for trunk?
I have a few comments on grammar and markup, but I can't comment
intelligently on whether the technical content is correct.
@@ -4013,24 +4015,94 @@ Top of 80387 floating-point stack (@code{%st(0)}).
@item u
Second from top of 80387 floating-point stack (@code{%st(1)}).
+@ifset INTERNALS
+@item Yk
+Any mask register that can be used as predicate, i.e. k1-k7.
s/predicate/a predicate/
Other places in this section use @code markup on literal register names.
+
+@item k
+Any mask register.
+@end ifset
+
@item y
Any MMX register.
@item x
Any SSE register.
+@item v
+Any EVEX encodable SSE register (@code{%xmm0-%xmm31}).
+
+@ifset INTERNALS
+@item w
+Any bound register.
+@end ifset
+
@item Yz
First SSE register (@code{%xmm0}).
@ifset INTERNALS
-@item Y2
-Any SSE register, when SSE2 is enabled.
-
@item Yi
Any SSE register, when SSE2 and inter-unit moves are enabled.
+@item Yj
+Any SSE register, when SSE2 and inter-unit moves from vector registers are
enabled.
+
@item Ym
Any MMX register, when inter-unit moves are enabled.
+
+@item Yn
+Any MMX register, when inter-unit moves from vector registers are enabled.
+
+@item Yp
+Any integer register when TARGET_PARTIAL_REG_STALL is disabled.
@code markup on that.
+
+@item Ya
+Any integer register when zero extensions with AND are disabled.
I'm not sure what "AND" is, but it probably needs @code markup too.
+
+@item Yb
+Any register that can be used as the GOT base when calling ___tls_get_addr:
@code{___tls_get_addr}
+that is, any general register except @code{a} and @code{sp} registers,
+for -fno-plt if linker supports it. Otherwise, @code{b} register.
@option{-fno-plt}
+
+@item Yf
+Any x87 register when 80387 FP arithmetic is enabled.
Is "FP" a literal feature name used in the processor documentation, or
do you just mean "floating-point arithmetic" here?
+
+@item Yr
+Lower SSE register when avoiding REX prefix and all SSE registers otherwise.
I don't know what "avoiding REX prefix" means, and don't see the string
"REX" in any other GCC documentation.
+
+@item Yv
+For AVX512VL, any EVEX encodable SSE register (@code{%xmm0-%xmm31}),
+otherwise any SSE register.
This should probably be "EVEX-encodable", whatever that means.
+
+@item Yh
+Any EVEX encodable SSE register, which has number factor of four.
Same here, but what is "number factor of four"? Also, if this is
supposed to designate a subset of the EVEX-encodable SSE registers
rather than describe all of them, you need "that" instead of "which".
+
+@item Bf
+Flags register operand.
+
+@item Bg
+GOT memory operand.
+
+@item Bm
+Vector memory operand.
+
+@item Bc
+Constant memory operand.
+
+@item Bn
+Memory operand without REX prefix.
+
+@item Bs
+Sibcall memory operand.
+
+@item Bw
+Call memory operand.
+
+@item Bz
+Constant call address operand.
+
+@item BC
+SSE constant -1 operand.
@end ifset
@item I
@@ -4068,11 +4140,37 @@ SSE constant zero operand.
to fit that range (for immediate operands in sign-extending x86-64
instructions).
+@item We
+32-bit signed integer constant, or a symbolic reference known
+to fit that range (for sign-extending conversion operations that
+require non-VOIDmode immediate operands).
@code{VOIDmode}.
+
+@item Wz
+32-bit unsigned integer constant, or a symbolic reference known
+to fit that range (for zero-extending conversion operations that
+require non-VOIDmode immediate operands).
Ditto.
+
+@item Wd
+128-bit integer constant where both the high and low 64-bit word
+of it satisfies the e constraint.
...where both the high and low 64-bit words satisfy the @code{e} constraint.
+
@item Z
32-bit unsigned integer constant, or a symbolic reference known
to fit that range (for immediate operands in zero-extending x86-64
instructions).
+@item Tv
+VSIB address operand.
+
+@item Ts
+Address operand without segment register.
+
+@item Ti
+MPX address operand without index.
+
+@item Tb
+MPX address operand without base.
+
@end table
@item Xstormy16---@file{config/stormy16/stormy16.h}
-Sandra
