Please find an updated patch in attachment. ChangeLog entry are now as follows:
*** gcc/ChangeLog ***
2017-07-06 Thomas Preud'homme <thomas.preudho...@arm.com>
* config/arm/arm-cpus.in (armv8-r): Add new entry.
* config/arm/arm-isa.h (ISA_ARMv8r): Define macro.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm.h (enum base_architecture): Add BASE_ARCH_8R
enumerator.
* doc/invoke.texi: Mention -march=armv8-r and its extensions.
*** gcc/testsuite/ChangeLog ***
2017-01-31 Thomas Preud'homme <thomas.preudho...@arm.com>
* lib/target-supports.exp: Generate
check_effective_target_arm_arch_v8r_ok, add_options_for_arm_arch_v8r
and check_effective_target_arm_arch_v8r_multilib.
*** libgcc/ChangeLog ***
2017-01-31 Thomas Preud'homme <thomas.preudho...@arm.com>
* config/arm/lib1funcs.S: Defined __ARM_ARCH__ to 8 for ARMv8-R.
Tested by building an arm-none-eabi GCC cross-compiler targetting
ARMv8-R.
Is this ok for stage1?
Best regards,
Thomas
Best regards,
Thomas
On 29/06/17 16:13, Thomas Preudhomme wrote:
Please ignore this patch. I'll respin the patch on a more recent GCC.
Best regards,
Thomas
On 29/06/17 14:55, Thomas Preudhomme wrote:
Hi,
This patch adds support for ARMv8-R architecture [1] which was recently
announced. User level instructions for ARMv8-R are the same as those in
ARMv8-A Aarch32 mode so this patch define ARMv8-R to have the same
features as ARMv8-A in ARM backend.
[1]
https://developer.arm.com/products/architecture/r-profile/docs/ddi0568/latest/arm-architecture-reference-manual-supplement-armv8-for-the-armv8-r-aarch32-architecture-profile
ChangeLog entries are as follow:
*** gcc/ChangeLog ***
2017-01-31 Thomas Preud'homme <thomas.preudho...@arm.com>
* config/arm/arm-cpus.in (armv8-r, armv8-r+rcr): Add new entry.
* config/arm/arm-cpu-cdata.h: Regenerate.
* config/arm/arm-cpu-data.h: Regenerate.
* config/arm/arm-isa.h (ISA_ARMv8r): Define macro.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm.h (enum base_architecture): Add BASE_ARCH_8R
enumerator.
* config/arm/bpabi.h (BE8_LINK_SPEC): Add entry for ARMv8-R and
ARMv8-R with CRC extensions.
* doc/invoke.texi: Mention -march=armv8-r and -march=armv8-r+crc
options. Document meaning of -march=armv8-r+rcr.
*** gcc/testsuite/ChangeLog ***
2017-01-31 Thomas Preud'homme <thomas.preudho...@arm.com>
* lib/target-supports.exp: Generate
check_effective_target_arm_arch_v8r_ok, add_options_for_arm_arch_v8r
and check_effective_target_arm_arch_v8r_multilib.
*** libgcc/ChangeLog ***
2017-01-31 Thomas Preud'homme <thomas.preudho...@arm.com>
* config/arm/lib1funcs.S: Defined __ARM_ARCH__ to 8 for ARMv8-R.
Tested by building an arm-none-eabi GCC cross-compiler targetting
ARMv8-R.
Is this ok for stage1?
Best regards,
Thomas
diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index 946d543ebb29416da9b4928161607cccacaa78a7..f35128acb7d68c6a0592355b9d3d56ee8f826aca 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -380,6 +380,22 @@ begin arch armv8-m.main
option nodsp remove bit_ARMv7em
end arch armv8-m.main
+begin arch armv8-r
+ tune for cortex-r4
+ tune flags CO_PROC
+ base 8R
+ profile R
+ isa ARMv8r
+ option crc add bit_crc32
+# fp.sp => fp-armv8 (d16); simd => simd + fp-armv8 + d32 + double precision
+# note: no fp option for fp-armv8 (d16) + double precision at the moment
+ option fp.sp add FP_ARMv8
+ option simd add FP_ARMv8 NEON
+ option crypto add FP_ARMv8 CRYPTO
+ option nocrypto remove ALL_CRYPTO
+ option nofp remove ALL_FP
+end arch armv8-r
+
begin arch iwmmxt
tune for iwmmxt
tune flags LDSCHED STRONG XSCALE
diff --git a/gcc/config/arm/arm-isa.h b/gcc/config/arm/arm-isa.h
index c0c2ccee330f2313951e980c5d399ae5d21005d6..0d66a0400c517668db023fc66ff43e26d43add51 100644
--- a/gcc/config/arm/arm-isa.h
+++ b/gcc/config/arm/arm-isa.h
@@ -127,6 +127,7 @@ enum isa_feature
#define ISA_ARMv8_2a ISA_ARMv8_1a, isa_bit_ARMv8_2
#define ISA_ARMv8m_base ISA_ARMv6m, isa_bit_ARMv8, isa_bit_cmse, isa_bit_tdiv
#define ISA_ARMv8m_main ISA_ARMv7m, isa_bit_ARMv8, isa_bit_cmse
+#define ISA_ARMv8r ISA_ARMv8a
/* List of all cryptographic extensions to stripout if crypto is
disabled. Currently, that's trivial, but we define it anyway for
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index 5e2df9dd0716293fb551b6582a8c9c2c46fdaa90..51678c2566e841894c5c0e9c613c8c0f832e9988 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -455,10 +455,13 @@ EnumValue
Enum(arm_arch) String(armv8-m.main) Value(30)
EnumValue
-Enum(arm_arch) String(iwmmxt) Value(31)
+Enum(arm_arch) String(armv8-r) Value(31)
EnumValue
-Enum(arm_arch) String(iwmmxt2) Value(32)
+Enum(arm_arch) String(iwmmxt) Value(32)
+
+EnumValue
+Enum(arm_arch) String(iwmmxt2) Value(33)
Enum
Name(arm_fpu) Type(enum fpu_type)
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index c803d4461c08436ef5f8468f6018e3226ccf33f8..315622212a5ce10d0c771535fe31f63c3be16444 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -384,7 +384,8 @@ enum base_architecture
BASE_ARCH_7EM = 7,
BASE_ARCH_8A = 8,
BASE_ARCH_8M_BASE = 8,
- BASE_ARCH_8M_MAIN = 8
+ BASE_ARCH_8M_MAIN = 8,
+ BASE_ARCH_8R = 8
};
/* The major revision number of the ARM Architecture implemented by the target. */
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 3e5cee8649ef9452e2a7e5a8603318ce11e2baff..d0b90503cedaae32bc83c7fd1fdd78b2a4d7184b 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -15218,6 +15218,7 @@ Permissible names are:
@samp{armv7}, @samp{armv7-a}, @samp{armv7ve},
@samp{armv8-a}, @samp{armv8.1-a}, @samp{armv8.2-a},
@samp{armv7-r},
+@samp{armv8-r},
@samp{armv6-m}, @samp{armv6s-m},
@samp{armv7-m}, @samp{armv7e-m},
@samp{armv8-m.base}, @samp{armv8-m.main},
@@ -15484,7 +15485,20 @@ The single- and double-precision floating-point instructions.
@item +nofp
Disable the floating-point extension.
+@end table
+@item armv8-r
+@table @samp
+@item +crc
+The Cyclic Redundancy Check (CRC) instructions.
+@item +simd
+The ARMv8 Advanced SIMD and floating-point instructions.
+@item +crypto
+The cryptographic instructions.
+@item +nocrypto
+Disable the cryptographic isntructions.
+@item +nofp
+Disable the floating-point, Advanced SIMD and cryptographic instructions.
@end table
@end table
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index fe5e77756404d603f04d674bb5ca872956d4b7ad..83d0c7ca441570dbf4d52641d12073f17d06e025 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -3890,7 +3890,8 @@ foreach { armfunc armflag armdefs } {
v8_2a "-march=armv8.2a" __ARM_ARCH_8A__
v8m_base "-march=armv8-m.base -mthumb -mfloat-abi=soft"
__ARM_ARCH_8M_BASE__
- v8m_main "-march=armv8-m.main -mthumb" __ARM_ARCH_8M_MAIN__ } {
+ v8m_main "-march=armv8-m.main -mthumb" __ARM_ARCH_8M_MAIN__
+ v8r "-march=armv8-r" __ARM_ARCH_8R__ } {
eval [string map [list FUNC $armfunc FLAG $armflag DEFS $armdefs ] {
proc check_effective_target_arm_arch_FUNC_ok { } {
if { [ string match "*-marm*" "FLAG" ] &&
diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S
index 89ebebcd68a790c6bec140e4a8bd5a3b44dce291..8d8c3cead5f77f6dfeb2887e68483119ee3a400a 100644
--- a/libgcc/config/arm/lib1funcs.S
+++ b/libgcc/config/arm/lib1funcs.S
@@ -109,7 +109,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#endif
#if defined(__ARM_ARCH_8A__) || defined(__ARM_ARCH_8M_BASE__) \
- || defined(__ARM_ARCH_8M_MAIN__)
+ || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8R__)
# define __ARM_ARCH__ 8
#endif