On Mon, Aug 14, 2017 at 04:28:25PM -0500, Peter Bergner wrote: > The following patch fixes a performance issue when loading/storing/moving > TImode values when using -mvsx-timode -mcpu=power7 with LRA. The problem is > that the vsx_le_permute_<mode> and vsx_le_perm_{load,store}_<mode> patterns > do no support TImode values in GPRs, and LRA is using these patterns to > fixup constraints, which ends up leading to really bad code gen as seen by > the test cases in the bug report. > > This patch fixes the bug by adding GPR support to the above patterns, as > well as a couple of peepholes that improve the code for loads and stores > to/from GPRs. > > This passed bootstrapping and regtesting with no regressions and Mike > ran this on SPEC2006 and found no performance regressions with it. > > Ok for trunk? Do we want this on the GCC 7 branch where LRA is on by default?
Okay for trunk (see nits below). For 7, okay after waiting a week or so for fallout, if you think it really helps there. > "@ > xxpermdi %x0,%x1,%x1,2 > lxvd2x %x0,%y1 > - stxvd2x %x1,%y0" > - [(set_attr "length" "4") > - (set_attr "type" "vecperm,vecload,vecstore")]) > + stxvd2x %x1,%y0 > + mr %0,%L1; mr %L0,%1 mr %0,%L1\;mr %L0,%1 etc. > +;; Peepholes to catch loads and stores for TImode if TImode landed in > +;; GPR registers on a little endian system. > +(define_peephole2 > + [(set (match_operand:VSX_TI 0 "int_reg_operand" "") You can leave out the default ""? > Index: gcc/testsuite/gcc.target/powerpc/pr72804.c > =================================================================== > --- gcc/testsuite/gcc.target/powerpc/pr72804.c (nonexistent) > +++ gcc/testsuite/gcc.target/powerpc/pr72804.c (working copy) > @@ -0,0 +1,25 @@ > +/* { dg-do compile { target { powerpc64*-*-* } } } */ powerpc64*-*-* is never correct, we are biarch. { target lp64 } instead? Thanks, Segher