Hi Charlie, I can't see any use for adding a bus width to tune params. There are many different buses in a modern CPU, so there is no such thing as a single "bus width".
What we need is to add separate costs for the different kinds of loads and stores. The timings for these depend mostly on the micro architecture. It would be difficult to tune for an MCU which supports 64-bit accesses to SRAM, 16-bit accesses to DRAM and which uses 32-bit buses otherwise, with different wait-states to ROM, flash and device memory... My feeling is we shouldn't try to cater for all possibilities as they are infinite and just focus on instruction timings as those are well defined. Wilco
