On Wed, Sep 13, 2017 at 03:02:55PM +0100, Jackson Woodruff wrote:
> Hi all,
>
> This patch changes pr62178.c so that it now scans
> for two `ldr`s, one into an `s` register, instead
> of a `ld1r` as before. Also add a scan for an mla
> instruction.
>
> The `ld1r` was needed when this should have generated
> a mla by vector. Now that we can generate an mla by
> element instruction and can load directly into the
> simd register, it is cheaper to not do the ld1r
> which needlessly duplicates the single element used
> across the whole vector register.
>
> The testcase passes now that
> https://gcc.gnu.org/ml/gcc-patches/2017-08/msg00048.html has been committed
>
> OK for trunk?
OK thanks, committed as revision 252086 on your behalf.
James
> 2017-09-13 Jackson Woodruff <jackson.woodr...@arm.com>
>
> * gcc.target/aarch64/pr62178.c: Updated testcase
> to scan for two ldrs and an mla.
> diff --git a/gcc/testsuite/gcc.target/aarch64/pr62178.c
> b/gcc/testsuite/gcc.target/aarch64/pr62178.c
> index
> b80ce68656076864bb71c76949cef5d7b530021a..1bf6d838d3a49ed5d8ecf9ae0157bd2a9159bfb4
> 100644
> --- a/gcc/testsuite/gcc.target/aarch64/pr62178.c
> +++ b/gcc/testsuite/gcc.target/aarch64/pr62178.c
> @@ -14,4 +14,6 @@ void foo (void) {
> }
> }
>
> -/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\."} } */
> +/* { dg-final { scan-assembler "ldr\\ts\[0-9\]+, \\\[x\[0-9\]+,
> \[0-9\]+\\\]!" } } */
> +/* { dg-final { scan-assembler "ldr\\tq\[0-9\]+, \\\[x\[0-9\]+\\\],
> \[0-9\]+" } } */
> +/* { dg-final { scan-assembler "mla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s,
> v\[0-9\]+\.s\\\[0\\\]" } } */
