Off list, Segher asked that I break the patch eliminating a shift right when
transfering SFmode from a vector register to a GPR register down into smaller
chunks. The power7 and power8 instructions that convert values in the double
precision format to single precision actually duplicate the 32-bits in the
first word and second word (the ISA says the second word is undefined). We are
in the process of issuing an update to ISA 3.0 to clarify that this will be the
required behavior going forward.
I have broken the patches down to 8 chunks. Some of the patch are just
cosmetic of things I noticed while doing the main patch. One patch eliminates
the shift. Another fixes up the peephole2 that optimizes putting a SFmode into
a union and then doing masking on the value. And the final patch updates the
tests that need to be changed.
I have verified that each of these sub-patches build, and after all 8 patches
have been applied, I did the full bootstrap and regresion test, and like the
previous combination patch there were no regressions. If only some of the
patches are applied, then there will be 3 regressions until the remaining
patches are applied.
This is patch #1. Can I check this into the trunk? I noticed without this
patch, sometimes the register allocator would do a store and then a load to
move a SImode value from a vector register to a GPR and sign extend it, instead
of doing the move and then the sign extension.
2017-09-25 Michael Meissner <meiss...@linux.vnet.ibm.com>
* config/rs6000/rs6000.md (extendsi<mode>2): Add a splitter to do
sign extension from a vector register to a GPR by doing a 32-bit
direct move and then an EXTSW.
(extendsi<mode>2 splitter): Likewise.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (revision 253157)
+++ gcc/config/rs6000/rs6000.md (working copy)
@@ -986,8 +986,11 @@ (define_insn_and_split "*extendhi<mode>2
(define_insn "extendsi<mode>2"
- [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,wl,wu,wj,wK,wH")
- (sign_extend:EXTSI (match_operand:SI 1 "lwa_operand"
"Y,r,Z,Z,r,wK,wH")))]
+ [(set (match_operand:EXTSI 0 "gpc_reg_operand"
+ "=r, r, wl, wu, wj, wK, wH, wr")
+
+ (sign_extend:EXTSI (match_operand:SI 1 "lwa_operand"
+ "Y, r, Z, Z, r, wK, wH, ?wIwH")))]
""
"@
lwa%U1%X1 %0,%1
@@ -996,10 +999,23 @@ (define_insn "extendsi<mode>2"
lxsiwax %x0,%y1
mtvsrwa %x0,%1
vextsw2d %0,%1
+ #
#"
- [(set_attr "type" "load,exts,fpload,fpload,mffgpr,vecexts,vecperm")
+ [(set_attr "type" "load,exts,fpload,fpload,mffgpr,vecexts,vecperm,mftgpr")
(set_attr "sign_extend" "yes")
- (set_attr "length" "4,4,4,4,4,4,8")])
+ (set_attr "length" "4,4,4,4,4,4,8,8")])
+
+(define_split
+ [(set (match_operand:DI 0 "int_reg_operand")
+ (sign_extend:DI (match_operand:SI 1 "vsx_register_operand")))]
+ "TARGET_DIRECT_MOVE_64BIT && reload_completed"
+ [(set (match_dup 2)
+ (match_dup 1))
+ (set (match_dup 0)
+ (sign_extend:DI (match_dup 2)))]
+{
+ operands[2] = gen_rtx_REG (SImode, reg_or_subregno (operands[0]));
+})
(define_split
[(set (match_operand:DI 0 "altivec_register_operand")
