From 7c163a89c01de27b8cefa6e889515effff5106fd Mon Sep 17 00:00:00 2001 From: "julia.koval" Date: Tue, 14 Mar 2017 13:21:37 +0300 Subject: [PATCH 11/14] VPDPBUSD instruction --- gcc/config.gcc | 6 +- gcc/config/i386/avx512vnniintrin.h | 66 ++++++ gcc/config/i386/avx512vnnivlintrin.h | 89 +++++++++ gcc/config/i386/i386-builtin.def | 42 ++++ gcc/config/i386/immintrin.h | 4 + gcc/config/i386/sse.md | 221 +++++++++++++++++++++ gcc/testsuite/gcc.target/i386/avx512-check.h | 3 + gcc/testsuite/gcc.target/i386/avx512f-vnni-1.c | 21 ++ gcc/testsuite/gcc.target/i386/avx512f-vpdpbusd-2.c | 70 +++++++ gcc/testsuite/gcc.target/i386/avx512vl-vnni-1.c | 27 +++ .../gcc.target/i386/avx512vl-vpdpbusd-2.c | 16 ++ gcc/testsuite/gcc.target/i386/i386.exp | 14 ++ 12 files changed, 577 insertions(+), 2 deletions(-) create mode 100644 gcc/config/i386/avx512vnniintrin.h create mode 100644 gcc/config/i386/avx512vnnivlintrin.h create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-vnni-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-vpdpbusd-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-vnni-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-vpdpbusd-2.c diff --git a/gcc/config.gcc b/gcc/config.gcc index 9b3a093..b2d31cd 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -379,7 +379,8 @@ i[34567]86-*-*) avx512vbmivlintrin.h avx5124fmapsintrin.h avx5124vnniwintrin.h avx512vpopcntdqintrin.h clwbintrin.h mwaitxintrin.h clzerointrin.h pkuintrin.h sgxintrin.h cetintrin.h - avx512vbmi2intrin.h avx512vbmi2vlintrin.h" + avx512vbmi2intrin.h avx512vbmi2vlintrin.h + avx512vnniintrin.h avx512vnnivlintrin.h" ;; x86_64-*-*) cpu_type=i386 @@ -404,7 +405,8 @@ x86_64-*-*) avx512vbmivlintrin.h avx5124fmapsintrin.h avx5124vnniwintrin.h avx512vpopcntdqintrin.h clwbintrin.h mwaitxintrin.h clzerointrin.h pkuintrin.h sgxintrin.h cetintrin.h - avx512vbmi2intrin.h avx512vbmi2vlintrin.h" + avx512vbmi2intrin.h avx512vbmi2vlintrin.h + avx512vnniintrin.h avx512vnnivlintrin.h" ;; ia64-*-*) extra_headers=ia64intrin.h diff --git a/gcc/config/i386/avx512vnniintrin.h b/gcc/config/i386/avx512vnniintrin.h new file mode 100644 index 0000000..9a48e28 --- /dev/null +++ b/gcc/config/i386/avx512vnniintrin.h @@ -0,0 +1,66 @@ +/* Copyright (C) 2013-2017 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +#ifndef _IMMINTRIN_H_INCLUDED +#error "Never use directly; include instead." +#endif + +#ifndef __AVX512VNNIINTRIN_H_INCLUDED +#define __AVX512VNNIINTRIN_H_INCLUDED + +#if !defined(__AVX512VNNI__) || !defined(__AVX512F__) +#pragma GCC push_options +#pragma GCC target("avx512vnni,avx512f") +#define __DISABLE_AVX512VNNI__ +#endif /* __AVX512VNNI__ */ + +extern __inline __m512i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_dpbusd_epi32 (__m512i __A, __m512i __B, __m512i __C) +{ + return (__m512i) __builtin_ia32_vpdpbusd_v16si ((__v16si)__A, (__v16si) __B, + (__v16si) __C); +} + +extern __inline __m512i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_dpbusd_epi32 (__m512i __A, __mmask16 __B, __m512i __C, __m512i __D) +{ + return (__m512i)__builtin_ia32_vpdpbusd_v16si_mask ((__v16si)__A, + (__v16si) __C, (__v16si) __D, (__mmask16)__B); +} + +extern __inline __m512i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_maskz_dpbusd_epi32 (__mmask16 __A, __m512i __B, __m512i __C, + __m512i __D) +{ + return (__m512i)__builtin_ia32_vpdpbusd_v16si_maskz ((__v16si)__B, + (__v16si) __C, (__v16si) __D, (__mmask16)__A); +} +#ifdef __DISABLE_AVX512VNNI__ +#undef __DISABLE_AVX512VNNI__ +#pragma GCC pop_options +#endif /* __DISABLE_AVX512VNNI__ */ + +#endif /* __AVX512VNNIINTRIN_H_INCLUDED */ diff --git a/gcc/config/i386/avx512vnnivlintrin.h b/gcc/config/i386/avx512vnnivlintrin.h new file mode 100644 index 0000000..b5fea90 --- /dev/null +++ b/gcc/config/i386/avx512vnnivlintrin.h @@ -0,0 +1,89 @@ +/* Copyright (C) 2013-2017 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +#ifndef _IMMINTRIN_H_INCLUDED +#error "Never use directly; include instead." +#endif + +#ifndef _AVX512VNNIVLINTRIN_H_INCLUDED +#define _AVX512VNNIVLINTRIN_H_INCLUDED + +#if !defined(__AVX512VL__) || !defined(__AVX512VNNI__) +#pragma GCC push_options +#pragma GCC target("avx512vnni,avx512vl") +#define __DISABLE_AVX512VNNIVL__ +#endif /* __AVX512VNNIVL__ */ + +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_dpbusd_epi32 (__m256i __A, __m256i __B, __m256i __C) +{ + return (__m256i) __builtin_ia32_vpdpbusd_v8si ((__v8si)__A, (__v8si) __B, + (__v8si) __C); +} + +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_dpbusd_epi32 (__m256i __A, __mmask8 __B, __m256i __C, __m256i __D) +{ + return (__m256i)__builtin_ia32_vpdpbusd_v8si_mask ((__v8si)__A, (__v8si) __C, + (__v8si) __D, (__mmask8)__B); +} + +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_dpbusd_epi32 (__mmask8 __A, __m256i __B, __m256i __C, __m256i __D) +{ + return (__m256i)__builtin_ia32_vpdpbusd_v8si_maskz ((__v8si)__B, + (__v8si) __C, (__v8si) __D, (__mmask8)__A); +} + +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_dpbusd_epi32 (__m128i __A, __m128i __B, __m128i __C) +{ + return (__m128i) __builtin_ia32_vpdpbusd_v4si ((__v4si)__A, (__v4si) __B, + (__v4si) __C); +} + +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask_dpbusd_epi32 (__m128i __A, __mmask8 __B, __m128i __C, __m128i __D) +{ + return (__m128i)__builtin_ia32_vpdpbusd_v4si_mask ((__v4si)__A, (__v4si) __C, + (__v4si) __D, (__mmask8)__B); +} + +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_maskz_dpbusd_epi32 (__mmask8 __A, __m128i __B, __m128i __C, __m128i __D) +{ + return (__m128i)__builtin_ia32_vpdpbusd_v4si_maskz ((__v4si)__B, + (__v4si) __C, (__v4si) __D, (__mmask8)__A); +} + +#ifdef __DISABLE_AVX512VNNIVL__ +#undef __DISABLE_AVX512VNNIVL__ +#pragma GCC pop_options +#endif /* __DISABLE_AVX512VNNIVL__ */ +#endif /* __DISABLE_AVX512VNNIVL__ */ diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index e437f2b..68661d1 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -2701,6 +2701,48 @@ BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v2di, "__builtin_ia32_vpshl BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v2di_mask, "__builtin_ia32_vpshldv_v2di_mask", IX86_BUILTIN_VPSHLDVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT) BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshldv_v2di_maskz, "__builtin_ia32_vpshldv_v2di_maskz", IX86_BUILTIN_VPSHLDVV2DI_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT) +/* VNNI */ + +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpbusd_v16si, "__builtin_ia32_vpdpbusd_v16si", IX86_BUILTIN_VPDPBUSDV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpbusd_v16si_mask, "__builtin_ia32_vpdpbusd_v16si_mask", IX86_BUILTIN_VPDPBUSDV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpbusd_v16si_maskz, "__builtin_ia32_vpdpbusd_v16si_maskz", IX86_BUILTIN_VPDPBUSDV16SI_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpbusd_v8si, "__builtin_ia32_vpdpbusd_v8si", IX86_BUILTIN_VPDPBUSDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpbusd_v8si_mask, "__builtin_ia32_vpdpbusd_v8si_mask", IX86_BUILTIN_VPDPBUSDV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpbusd_v8si_maskz, "__builtin_ia32_vpdpbusd_v8si_maskz", IX86_BUILTIN_VPDPBUSDV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpbusd_v4si, "__builtin_ia32_vpdpbusd_v4si", IX86_BUILTIN_VPDPBUSDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpbusd_v4si_mask, "__builtin_ia32_vpdpbusd_v4si_mask", IX86_BUILTIN_VPDPBUSDV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpbusd_v4si_maskz, "__builtin_ia32_vpdpbusd_v4si_maskz", IX86_BUILTIN_VPDPBUSDV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT) + +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpbusds_v16si, "__builtin_ia32_vpdpbusds_v16si", IX86_BUILTIN_VPDPBUSDSV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpbusds_v16si_mask, "__builtin_ia32_vpdpbusds_v16si_mask", IX86_BUILTIN_VPDPBUSDSV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpbusds_v16si_maskz, "__builtin_ia32_vpdpbusds_v16si_maskz", IX86_BUILTIN_VPDPBUSDSV16SI_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpbusds_v8si, "__builtin_ia32_vpdpbusds_v8si", IX86_BUILTIN_VPDPBUSDSV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpbusds_v8si_mask, "__builtin_ia32_vpdpbusds_v8si_mask", IX86_BUILTIN_VPDPBUSDSV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpbusds_v8si_maskz, "__builtin_ia32_vpdpbusds_v8si_maskz", IX86_BUILTIN_VPDPBUSDSV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpbusds_v4si, "__builtin_ia32_vpdpbusds_v4si", IX86_BUILTIN_VPDPBUSDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpbusds_v4si_mask, "__builtin_ia32_vpdpbusds_v4si_mask", IX86_BUILTIN_VPDPBUSDSV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpbusds_v4si_maskz, "__builtin_ia32_vpdpbusds_v4si_maskz", IX86_BUILTIN_VPDPBUSDSV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT) + +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpwssd_v16si, "__builtin_ia32_vpdpwssd_v16si", IX86_BUILTIN_VPDPWSSDV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpwssd_v16si_mask, "__builtin_ia32_vpdpwssd_v16si_mask", IX86_BUILTIN_VPDPWSSDV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpwssd_v16si_maskz, "__builtin_ia32_vpdpwssd_v16si_maskz", IX86_BUILTIN_VPDPWSSDV16SI_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpwssd_v8si, "__builtin_ia32_vpdpwssd_v8si", IX86_BUILTIN_VPDPWSSDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpwssd_v8si_mask, "__builtin_ia32_vpdpwssd_v8si_mask", IX86_BUILTIN_VPDPWSSDV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpwssd_v8si_maskz, "__builtin_ia32_vpdpwssd_v8si_maskz", IX86_BUILTIN_VPDPWSSDV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpwssd_v4si, "__builtin_ia32_vpdpwssd_v4si", IX86_BUILTIN_VPDPWSSDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpwssd_v4si_mask, "__builtin_ia32_vpdpwssd_v4si_mask", IX86_BUILTIN_VPDPWSSDV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpwssd_v4si_maskz, "__builtin_ia32_vpdpwssd_v4si_maskz", IX86_BUILTIN_VPDPWSSDV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT) + +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpwssds_v16si, "__builtin_ia32_vpdpwssds_v16si", IX86_BUILTIN_VPDPWSSDSV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpwssds_v16si_mask, "__builtin_ia32_vpdpwssds_v16si_mask", IX86_BUILTIN_VPDPWSSDSV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpwssds_v16si_maskz, "__builtin_ia32_vpdpwssds_v16si_maskz", IX86_BUILTIN_VPDPWSSDSV16SI_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpwssds_v8si, "__builtin_ia32_vpdpwssds_v8si", IX86_BUILTIN_VPDPWSSDSV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpwssds_v8si_mask, "__builtin_ia32_vpdpwssds_v8si_mask", IX86_BUILTIN_VPDPWSSDSV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpwssds_v8si_maskz, "__builtin_ia32_vpdpwssds_v8si_maskz", IX86_BUILTIN_VPDPWSSDSV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpwssds_v4si, "__builtin_ia32_vpdpwssds_v4si", IX86_BUILTIN_VPDPWSSDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpwssds_v4si_mask, "__builtin_ia32_vpdpwssds_v4si_mask", IX86_BUILTIN_VPDPWSSDSV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT) +BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpwssds_v4si_maskz, "__builtin_ia32_vpdpwssds_v4si_maskz", IX86_BUILTIN_VPDPWSSDSV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT) + BDESC_END (ARGS2, SPECIAL_ARGS2) BDESC_FIRST (special_args2, SPECIAL_ARGS2, OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_compressstorev64qi_mask, "__builtin_ia32_compressstoreuqi512_mask", IX86_BUILTIN_PCOMPRESSBSTORE512, UNKNOWN, (int) VOID_FTYPE_PV64QI_V64QI_UDI) diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h index 294c5bc..b2a254f 100644 --- a/gcc/config/i386/immintrin.h +++ b/gcc/config/i386/immintrin.h @@ -78,6 +78,10 @@ #include +#include + +#include + #include #include diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 89ccdf0..7eeaf85 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -163,6 +163,12 @@ UNSPEC_VPSHRD UNSPEC_VPSHRDV UNSPEC_VPSHLDV + + ;; For AVX512VNNI support + UNSPEC_VPMADDUBSWACCD + UNSPEC_VPMADDUBSWACCSSD + UNSPEC_VPMADDWDACCD + UNSPEC_VPMADDWDACCSSD ]) (define_c_enum "unspecv" [ @@ -20364,3 +20370,218 @@ "vpshldv\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }" [(set_attr ("prefix") ("evex")) (set_attr "mode" "")]) + +(define_insn "vpdpbusd_" + [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v") + (unspec:VI4_AVX512VL + [(match_operand:VI4_AVX512VL 1 "register_operand" "0") + (match_operand:VI4_AVX512VL 2 "register_operand" "v") + (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm") +] UNSPEC_VPMADDUBSWACCD))] + "TARGET_AVX512VNNI" + "vpdpbusd\t{%3, %2, %0|%0, %2, %3 }" + [(set_attr ("prefix") ("evex"))]) + +(define_insn "vpdpbusd__mask" + [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v") + (vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL + [(match_operand:VI4_AVX512VL 1 "register_operand" "0") + (match_operand:VI4_AVX512VL 2 "register_operand" "v") + (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm") + ] UNSPEC_VPMADDUBSWACCD) + (match_dup 1) + (match_operand: 4 "register_operand" "Yk")) +)] + "TARGET_AVX512VNNI" + "vpdpbusd\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }" + [(set_attr ("prefix") ("evex"))]) + +(define_expand "vpdpbusd__maskz" + [(match_operand:VI4_AVX512VL 0 "register_operand") + (match_operand:VI4_AVX512VL 1 "register_operand") + (match_operand:VI4_AVX512VL 2 "register_operand") + (match_operand:VI4_AVX512VL 3 "nonimmediate_operand") + (match_operand: 4 "register_operand")] + "TARGET_AVX512VNNI" +{ + emit_insn (gen_vpdpbusd__maskz_1 ( + operands[0], operands[1], operands[2], operands[3], + CONST0_RTX (mode), operands[4])); + DONE; +}) + +(define_insn "vpdpbusd__maskz_1" + [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v") + (vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL + [(match_operand:VI4_AVX512VL 1 "register_operand" "0") + (match_operand:VI4_AVX512VL 2 "register_operand" "v") + (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm") + ] UNSPEC_VPMADDUBSWACCD) + (match_operand:VI4_AVX512VL 4 "const0_operand" "C") + (match_operand: 5 "register_operand" "Yk")) +)] + "TARGET_AVX512VNNI" + "vpdpbusd\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }" + [(set_attr ("prefix") ("evex"))]) + + +(define_insn "vpdpbusds_" + [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v") + (unspec:VI4_AVX512VL + [(match_operand:VI4_AVX512VL 1 "register_operand" "0") + (match_operand:VI4_AVX512VL 2 "register_operand" "v") + (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm") +] UNSPEC_VPMADDUBSWACCSSD))] + "TARGET_AVX512VNNI" + "vpdpbusds\t{%3, %2, %0|%0, %2, %3 }" + [(set_attr ("prefix") ("evex"))]) + +(define_insn "vpdpbusds__mask" + [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v") + (vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL + [(match_operand:VI4_AVX512VL 1 "register_operand" "0") + (match_operand:VI4_AVX512VL 2 "register_operand" "v") + (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm") + ] UNSPEC_VPMADDUBSWACCSSD) + (match_dup 1) + (match_operand: 4 "register_operand" "Yk")) +)] + "TARGET_AVX512VNNI" + "vpdpbusds\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }" + [(set_attr ("prefix") ("evex"))]) + +(define_expand "vpdpbusds__maskz" + [(match_operand:VI4_AVX512VL 0 "register_operand") + (match_operand:VI4_AVX512VL 1 "register_operand") + (match_operand:VI4_AVX512VL 2 "register_operand") + (match_operand:VI4_AVX512VL 3 "nonimmediate_operand") + (match_operand: 4 "register_operand")] + "TARGET_AVX512VNNI" +{ + emit_insn (gen_vpdpbusds__maskz_1 ( + operands[0], operands[1], operands[2], operands[3], + CONST0_RTX (mode), operands[4])); + DONE; +}) + +(define_insn "vpdpbusds__maskz_1" + [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v") + (vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL + [(match_operand:VI4_AVX512VL 1 "register_operand" "0") + (match_operand:VI4_AVX512VL 2 "register_operand" "v") + (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm") + ] UNSPEC_VPMADDUBSWACCSSD) + (match_operand:VI4_AVX512VL 4 "const0_operand" "C") + (match_operand: 5 "register_operand" "Yk")) +)] + "TARGET_AVX512VNNI" + "vpdpbusds\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }" + [(set_attr ("prefix") ("evex"))]) + + +(define_insn "vpdpwssd_" + [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v") + (unspec:VI4_AVX512VL + [(match_operand:VI4_AVX512VL 1 "register_operand" "0") + (match_operand:VI4_AVX512VL 2 "register_operand" "v") + (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm") +] UNSPEC_VPMADDWDACCD))] + "TARGET_AVX512VNNI" + "vpdpwssd\t{%3, %2, %0|%0, %2, %3 }" + [(set_attr ("prefix") ("evex"))]) + +(define_insn "vpdpwssd__mask" + [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v") + (vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL + [(match_operand:VI4_AVX512VL 1 "register_operand" "0") + (match_operand:VI4_AVX512VL 2 "register_operand" "v") + (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm") + ] UNSPEC_VPMADDWDACCD) + (match_dup 1) + (match_operand: 4 "register_operand" "Yk")) +)] + "TARGET_AVX512VNNI" + "vpdpwssd\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }" + [(set_attr ("prefix") ("evex"))]) + +(define_expand "vpdpwssd__maskz" + [(match_operand:VI4_AVX512VL 0 "register_operand") + (match_operand:VI4_AVX512VL 1 "register_operand") + (match_operand:VI4_AVX512VL 2 "register_operand") + (match_operand:VI4_AVX512VL 3 "nonimmediate_operand") + (match_operand: 4 "register_operand")] + "TARGET_AVX512VNNI" +{ + emit_insn (gen_vpdpwssd__maskz_1 ( + operands[0], operands[1], operands[2], operands[3], + CONST0_RTX (mode), operands[4])); + DONE; +}) + +(define_insn "vpdpwssd__maskz_1" + [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v") + (vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL + [(match_operand:VI4_AVX512VL 1 "register_operand" "0") + (match_operand:VI4_AVX512VL 2 "register_operand" "v") + (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm") + ] UNSPEC_VPMADDWDACCD) + (match_operand:VI4_AVX512VL 4 "const0_operand" "C") + (match_operand: 5 "register_operand" "Yk")) +)] + "TARGET_AVX512VNNI" + "vpdpwssd\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }" + [(set_attr ("prefix") ("evex"))]) + + +(define_insn "vpdpwssds_" + [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v") + (unspec:VI4_AVX512VL + [(match_operand:VI4_AVX512VL 1 "register_operand" "0") + (match_operand:VI4_AVX512VL 2 "register_operand" "v") + (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm") +] UNSPEC_VPMADDWDACCSSD))] + "TARGET_AVX512VNNI" + "vpdpwssds\t{%3, %2, %0|%0, %2, %3 }" + [(set_attr ("prefix") ("evex"))]) + +(define_insn "vpdpwssds__mask" + [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v") + (vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL + [(match_operand:VI4_AVX512VL 1 "register_operand" "0") + (match_operand:VI4_AVX512VL 2 "register_operand" "v") + (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm") + ] UNSPEC_VPMADDWDACCSSD) + (match_dup 1) + (match_operand: 4 "register_operand" "Yk")) +)] + "TARGET_AVX512VNNI" + "vpdpwssds\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }" + [(set_attr ("prefix") ("evex"))]) + +(define_expand "vpdpwssds__maskz" + [(match_operand:VI4_AVX512VL 0 "register_operand") + (match_operand:VI4_AVX512VL 1 "register_operand") + (match_operand:VI4_AVX512VL 2 "register_operand") + (match_operand:VI4_AVX512VL 3 "nonimmediate_operand") + (match_operand: 4 "register_operand")] + "TARGET_AVX512VNNI" +{ + emit_insn (gen_vpdpwssds__maskz_1 ( + operands[0], operands[1], operands[2], operands[3], + CONST0_RTX (mode), operands[4])); + DONE; +}) + +(define_insn "vpdpwssds__maskz_1" + [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v") + (vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL + [(match_operand:VI4_AVX512VL 1 "register_operand" "0") + (match_operand:VI4_AVX512VL 2 "register_operand" "v") + (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm") + ] UNSPEC_VPMADDWDACCSSD) + (match_operand:VI4_AVX512VL 4 "const0_operand" "C") + (match_operand: 5 "register_operand" "Yk")) +)] + "TARGET_AVX512VNNI" + "vpdpwssds\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }" + [(set_attr ("prefix") ("evex"))]) diff --git a/gcc/testsuite/gcc.target/i386/avx512-check.h b/gcc/testsuite/gcc.target/i386/avx512-check.h index 3f720c2..d7533f5 100644 --- a/gcc/testsuite/gcc.target/i386/avx512-check.h +++ b/gcc/testsuite/gcc.target/i386/avx512-check.h @@ -78,6 +78,9 @@ main () #ifdef AVX512VBMI2 && (ecx & bit_AVX512VBMI2) #endif +#ifdef AVX512VNNI + && (ecx & bit_AVX512VNNI) +#endif && avx512f_os_support ()) { DO_TEST (); diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vnni-1.c b/gcc/testsuite/gcc.target/i386/avx512f-vnni-1.c new file mode 100644 index 0000000..32fc8a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-vnni-1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512f -mavx512vnni -mavx512bw -O2" } */ +/* { dg-final { scan-assembler-times "vpdpbusd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpbusd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpbusd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m512i x,y,z,z1; +volatile __mmask32 m32; +volatile __mmask16 m16; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + x = _mm512_dpbusd_epi32 (x, y, z); + x = _mm512_mask_dpbusd_epi32 (x, m16, y, z); + x = _mm512_maskz_dpbusd_epi32 (m16, x, y, z); + +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vpdpbusd-2.c b/gcc/testsuite/gcc.target/i386/avx512f-vpdpbusd-2.c new file mode 100644 index 0000000..fb16358 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-vpdpbusd-2.c @@ -0,0 +1,70 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512f -mavx512vnni" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-require-effective-target avx512vnni } */ + +#define AVX512F + +#define AVX512VNNI +#include "avx512f-helper.h" + +#define SIZE (AVX512F_LEN / 8) +#define SIZE_RES (AVX512F_LEN / 32) + +#include "avx512f-mask-type.h" + +static void +CALC (int *r, int *dst, unsigned char *s1, char *s2) +{ + short tempres[SIZE]; + for (int i = 0; i < SIZE; i++) { + tempres[i] = ((unsigned short)(s1[i]) * (short)(s2[i])); + } + for (int i = 0; i < SIZE_RES; i++) { + long long test = (long long)dst[i] + tempres[i*4] + tempres[i*4 + 1] + tempres[i*4 + 2] + tempres[i*4 + 3]; + r[i] = test; + } +} + +void +TEST (void) +{ + int i; + UNION_TYPE (AVX512F_LEN, i_d) res1, res2, res3; + UNION_TYPE (AVX512F_LEN, i_ub) src1; + UNION_TYPE (AVX512F_LEN, i_b) src2; + MASK_TYPE mask = MASK_VALUE; + int res_ref[SIZE_RES], res_ref2[SIZE_RES]; + + for (i = 0; i < SIZE; i++) + { + int sign = i % 2 ? 1 : -1; + src1.a[i] = 10 + 3*i*i + sign; + src2.a[i] = sign*10*i*i; + } + + for (i = 0; i < SIZE_RES; i++) + { + res1.a[i] = 0x7FFFFFFF; + res2.a[i] = DEFAULT_VALUE; + res3.a[i] = DEFAULT_VALUE; + } + + CALC (res_ref, res1.a, src1.a, src2.a); + CALC (res_ref2, res2.a, src1.a, src2.a); + + res1.x = INTRINSIC (_dpbusd_epi32) (res1.x, src1.x, src2.x); + res2.x = INTRINSIC (_mask_dpbusd_epi32) (res2.x, mask, src1.x, src2.x); + res3.x = INTRINSIC (_maskz_dpbusd_epi32) (mask, res3.x, src1.x, src2.x); + + if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref)) + abort (); + + MASK_MERGE (i_d) (res_ref2, mask, SIZE_RES); + if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref2)) + abort (); + + MASK_ZERO (i_d) (res_ref2, mask, SIZE_RES); + if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref2)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vnni-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vnni-1.c new file mode 100644 index 0000000..bc18c63 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vnni-1.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512vl -mavx512vnni -mavx512bw -O2" } */ +/* { dg-final { scan-assembler-times "vpdpbusd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpbusd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpbusd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpbusd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpbusd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpbusd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m256i x,y,z; +volatile __m128i x_,y_,z_; +volatile __mmask32 m; + +void extern +avx512f_test (void) +{ + x = _mm256_dpbusd_epi32 (x, y, z); + x = _mm256_mask_dpbusd_epi32 (x, m, y, z); + x = _mm256_maskz_dpbusd_epi32 (m, x, y, z); + + x_ = _mm_dpbusd_epi32 (x_, y_, z_); + x_ = _mm_mask_dpbusd_epi32 (x_, m, y_, z_); + x_ = _mm_maskz_dpbusd_epi32 (m, x_, y_, z_); + +} diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpdpbusd-2.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpdpbusd-2.c new file mode 100644 index 0000000..81be233 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpdpbusd-2.c @@ -0,0 +1,16 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512vnni -mavx512vl" } */ +/* { dg-require-effective-target avx512vl } */ +/* { dg-require-effective-target avx512vnni } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512f-vpdpbusd-2.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512f-vpdpbusd-2.c" diff --git a/gcc/testsuite/gcc.target/i386/i386.exp b/gcc/testsuite/gcc.target/i386/i386.exp index da66565..9ae2d16 100644 --- a/gcc/testsuite/gcc.target/i386/i386.exp +++ b/gcc/testsuite/gcc.target/i386/i386.exp @@ -437,6 +437,20 @@ proc check_effective_target_avx512vbmi2 { } { } "-mavx512vbmi2 -mavx512vl" ] } +# Return 1 if avx512vbmi2 instructions can be compiled. +proc check_effective_target_avx512vnni { } { + return [check_no_compiler_messages avx512vnni object { + typedef int __v16si __attribute__ ((__vector_size__ (64))); + + __v16si + _mm_mask_compress_epi8 (__v16si __A, __v16si __B, __v16si __C) + { + return (__v16si) __builtin_ia32_vpdpbusd_v16si ((__v16si)__A, + (__v16si)__B, + (__v16si)__C); + } + } "-mavx512vnni -mavx512f" ] +} # If a testcase doesn't have special options, use these. global DEFAULT_CFLAGS -- 2.5.5