On 08/24/2017 07:18 AM, Jozef Lawrynowicz wrote: > As reported in PR78554, attempting to store an __int20 address in memory > causes an ICE due to an invalid insn. This only occurs at optimisation > levels higher than -O0 because these optimisation levels pass > -ftree-ter, which causes the compiler to try and do the store in > one instruction. > The issue in the insn is that a SUBREG references a SYMBOL_REF. > > I guess the compiler gets into this situation because it assumes that > it can execute a move instruction where both src and dst are in memory, > but this isn't possible with __int20. GCC doesn't really make this assumption, but it does rely on the target's movXX expanders to handle generating correct code for a mem->mem move.
Commonly on risc targets what you'll see is a movXX expanders like this: (define_expand "movsi" [(set (match_operand:SI 0 "nonimmediate_operand") (match_operand:SI 1 "general_operand"))] "" { /* One of the ops has to be in a register. */ if (!register_operand (operand1, SImode) && !register_operand (operand0, SImode)) operands[1] = force_reg (SImode, operand1); > > The attached patch prevents a instance of SUBREG being created where the > subword is a SYMBOL_REF. > > If the patch is acceptable, I would appreciate if someone could commit > it for me, as I do not have write access. I was going to look deeper at this, but can't as the trunk currently aborts in init_derived_machine_modes when compiling the testcase. Presumably something about Richard S's work is busted when it comes to dealing with partial-word stuff. I'll ping Richard S. to take a looksie. Jeff