On 01/09/18 18:50, Richard Earnshaw (lists) wrote: > On 09/01/18 17:36, Bernd Edlinger wrote: >> Richard Earnshaw wrote: >> > Let me give an example, we use the generic code expansion if we >> > encounter the builtin when generating code for Thumb on pre-ARMv7 >> > devices. We don't have instructions in 'thumb1' to guard against >> > speculation and we really want to warn users that they've done this (it >> > might be a mistake in how they're invoking the compiler). >> >> Instead of this warning in one of the unsupported cases, could you use >> the DSB SYS + ISB barrier as the white paper suggests? >> >> >> Bernd. > > Thumb1 doesn't have those instructions. >
I don't know if it helps, but a few years ago I have written some assembler macros that allow to temporarily switch from THUMB to ARM mode and back on an ARMv5 target, that used to worked quite well: # define HAL_ARM_MODE() ";" \ " .align 2;" \ " bx pc;" \ " nop;" \ " .code 32;" # define HAL_THUMB_MODE(_scratch_) ";" \ " orr " #_scratch_ ",pc,#1;" \ " bx " #_scratch_ ";" \ " .code 16;" #define HAL_DISABLE_INTERRUPTS(_old_) \ asm volatile ( \ HAL_ARM_MODE() \ "mrs %0,cpsr;" \ "orr r3,%0,%1;" \ "msr cpsr,r3" \ HAL_THUMB_MODE(r3) \ : "=r"(_old_) \ : "i"(CPSR_INTR_MASK) \ : "r3" \ ); #define HAL_ENABLE_INTERRUPTS() \ asm volatile ( \ HAL_ARM_MODE() \ "mrs r3,cpsr;" \ "bic r3,r3,%0;" \ "msr cpsr,r3" \ HAL_THUMB_MODE(r3) \ : \ : "i"(CPSR_INTR_MASK) \ : "r3" \ ); So the the switch back macro just needed a scratch register, that's all. Bernd.