Hi,
Update the vec-neg-longlong folding tests to handle codegen variations
as seen between p8 and p9 targets.
This breaks out the tests into p7,p8,p9 versions of the same, while moving the
common testcase content into a #included header.
sniff-tested across power systems (P6,P8,P9)
This cleans up a handful of errors seen on P9.
OK for trunk?
THanks,
-Will
[testsuite]
2018-01-24 Will Schmidt <will_schm...@vnet.ibm.com>
* gcc.target/powerpcfold-vec-neg-longlong.h: New.
* gcc.target/powerpc/fold-vec-neg-longlong.p8.c: New.
* gcc.target/powerpc/fold-vec-neg-longlong.p9.c: New.
* gcc.target/powerpc/fold-vec-neg-longlong.c: Delete.
* gcc.target/powerpc/fold-vec-neg-int.c: Remove scan-assembler stanzas.
* gcc.target/powerpc/fold-vec-neg-int.p7.c: New.
* gcc.target/powerpc/fold-vec-neg-int.p8.c: New.
* gcc.target/powerpc/fold-vec-neg-int.p9.c: New.
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.c
index d6ca128..4f35856 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.c
@@ -11,8 +11,6 @@ vector signed int
test1 (vector signed int x)
{
return vec_neg (x);
}
-/* { dg-final { scan-assembler-times "xxspltib|vspltisw|vxor" 1 } } */
-/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */
-/* { dg-final { scan-assembler-times "vmaxsw" 0 } } */
+/* Scan-assembler stanzas have been moved to fold-vec-neg-int.p*.c tests. */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.p7.c
new file mode 100644
index 0000000..8e99de3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.p7.c
@@ -0,0 +1,19 @@
+/* Verify that overloaded built-ins for vec_neg with int
+ inputs produce the right code when -mcpu=power7 is specified. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -mcpu=power7" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } {
"-mcpu=power7" } } */
+
+#include <altivec.h>
+
+vector signed int
+test1 (vector signed int x)
+{
+ return vec_neg (x);
+}
+
+/* { dg-final { scan-assembler-times "xxspltib|vspltisw|vxor" 1 } } */
+/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsw" 0 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.p8.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.p8.c
new file mode 100644
index 0000000..91067ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.p8.c
@@ -0,0 +1,19 @@
+/* Verify that overloaded built-ins for vec_neg with int
+ inputs produce the right code when -mcpu=power8 is specified. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -mcpu=power8" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } {
"-mcpu=power8" } } */
+
+#include <altivec.h>
+
+vector signed int
+test1 (vector signed int x)
+{
+ return vec_neg (x);
+}
+
+/* { dg-final { scan-assembler-times "xxspltib|vspltisw|vxor" 1 } } */
+/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsw" 0 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.p9.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.p9.c
new file mode 100644
index 0000000..44732c8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.p9.c
@@ -0,0 +1,18 @@
+/* Verify that overloaded built-ins for vec_neg with int
+ inputs produce the right code when -mcpu=power9 is specified. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -mcpu=power9" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } {
"-mcpu=power9" } } */
+
+#include <altivec.h>
+
+vector signed int
+test1 (vector signed int x)
+{
+ return vec_neg (x);
+}
+
+/* { dg-final { scan-assembler-times "vnegw" 1 } } */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.c
deleted file mode 100644
index 48f7178..0000000
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Verify that overloaded built-ins for vec_neg with long long
- inputs produce the right code. */
-
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mpower8-vector -O2" } */
-
-#include <altivec.h>
-
-vector signed long long
-test3 (vector signed long long x)
-{
- return vec_neg (x);
-}
-
-/* { dg-final { scan-assembler-times "xxspltib|vspltisw" 1 } } */
-/* { dg-final { scan-assembler-times "vsubudm" 1 } } */
-/* { dg-final { scan-assembler-times "vmaxsd" 0 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.h
b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.h
new file mode 100644
index 0000000..53312ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.h
@@ -0,0 +1,17 @@
+/* Verify that overloaded built-ins for vec_neg with long long
+ inputs produce the right code. */
+
+/* vec_neg testcase, included by fold-vec-neg-longlong.p*.c */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mpower8-vector -O2" } */
+
+#include <altivec.h>
+
+vector signed long long
+test3 (vector signed long long x)
+{
+ return vec_neg (x);
+}
+
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.p8.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.p8.c
new file mode 100644
index 0000000..90f9abc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.p8.c
@@ -0,0 +1,14 @@
+/* Verify that overloaded built-ins for vec_neg with long long
+ inputs produce the right code. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mpower8-vector -mcpu=power8 -O2" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } {
"-mcpu=power8" } } */
+
+
+#include "fold-vec-neg-longlong.h"
+
+/* { dg-final { scan-assembler-times "xxspltib|vspltisw" 1 } } */
+/* { dg-final { scan-assembler-times "vsubudm" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsd" 0 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.p9.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.p9.c
new file mode 100644
index 0000000..39fbaf1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.p9.c
@@ -0,0 +1,14 @@
+/* Verify that overloaded built-ins for vec_neg with long long
+ inputs produce the right code. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mcpu=power9 -O2" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } {
"-mcpu=power9" } } */
+
+#include "fold-vec-neg-longlong.h"
+
+
+/* { dg-final { scan-assembler-times "vnegd" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxsd" 0 } } */
+
