> By QImode addition, do you mean:
>    (set (subreg:QI (reg:SI X1) N)
>       (plus:QI (subreg:QI (reg:SI X2) N)
>                (subreg:QI (reg:SI X3) N)))
> ?


> I thought the point was instead that the target expected such ops
> to be done on word_mode, even if the values involved are naturally QImode:
>    (set (subreg:SI (reg:QI Y1) 0)
>       (plus:SI (subreg:SI (reg:QI Y2) 0)
>                (subreg:SI (reg:QI Y3) 0)))

But that's not what the implementation of WORD_REGISTER_OPERATIONS does; IOW 
you'll get the above from expand_binop without the macro if there is no addqi.

> Most RISC/WORD_REGISTER_OPERATIONS targets wouldn't provide QImode
> addition patterns, so the first insn seems unlikely.

Indeed, SImode on 64-bit RISC targets should have been more realistic, but I 
didn't want to give a 64-bit example.

Eric Botcazou

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