>+/* STRD in ARM mode needs consecutive registers to be stored. This function
>+ keeps accumulating non-consecutive registers until first consecutive
>register
numchar > 80.
>+ pair is found. It then generates multi-reg PUSH for all accumulated
>+ registers, and then generates STRD with write-back for consecutive register
>+ pair. This process is repeated until all the registers are stored on
>stack.
And again.
>+ multi-reg PUSH takes care of lone registers as well. */
s/multi-reg/Multi register
>+static void
>+arm_emit_strd_push (unsigned long saved_regs_mask)
How different is this from the thumb2 version you sent out in Patch 03/05 ?
>+{
>+ int num_regs = 0;
>+ int i, j;
>+ rtx par = NULL_RTX;
>+ rtx dwarf = NULL_RTX;
>+ rtx insn = NULL_RTX;
>+ rtx tmp, tmp1;
>+ unsigned long regs_to_be_pushed_mask;
>+
>+ for (i = 0; i <= LAST_ARM_REGNUM; i++)
>+ if (saved_regs_mask & (1 << i))
>+ num_regs++;
>+
>+ gcc_assert (num_regs && num_regs <= 16);
>+
>+ for (i=0, j = LAST_ARM_REGNUM, regs_to_be_pushed_mask = 0; i < num_regs;
>j--)
>+ /* Var j iterates over all registers to gather all registers in
>+ saved_regs_mask. Var i is used to count number of registers stored on
>+ stack. regs_to_be_pushed_mask accumulates non-consecutive registers
>+ that can be pushed using multi-reg PUSH before STRD is generated. */
Comment above loop.
<...snip...>
>@@ -15958,7 +16081,8 @@ arm_get_frame_offsets (void)
> use 32-bit push/pop instructions. */
> if (! any_sibcall_uses_r3 ()
> && arm_size_return_regs () <= 12
>- && (offsets->saved_regs_mask & (1 << 3)) == 0)
>+ && (offsets->saved_regs_mask & (1 << 3)) == 0
>+ && (TARGET_THUMB2 || !current_tune->prefer_ldrd_strd))
Not sure I completely follow this change yet.
>@@ -16427,9 +16551,12 @@ arm_expand_prologue (void)
> }
> }
>
>- if (TARGET_THUMB2 && current_tune->prefer_ldrd_strd && !optimize_size)
>+ if (current_tune->prefer_ldrd_strd && !optimize_size)
s/optimize_size/optimize_function_for_size ()
> {
>- thumb2_emit_strd_push (live_regs_mask);
>+ if (TARGET_THUMB2)
>+ thumb2_emit_strd_push (live_regs_mask);
>+ else
>+ arm_emit_strd_push (live_regs_mask);
> }
> else
> {
>diff --git a/gcc/config/arm/ldmstm.md b/gcc/config/arm/ldmstm.md
>index e3dcd4f..3c729bb 100644
>--- a/gcc/config/arm/ldmstm.md
>+++ b/gcc/config/arm/ldmstm.md
>@@ -73,6 +73,42 @@
> [(set_attr "type" "store2")
> (set_attr "predicable" "yes")])
>
>+(define_insn "*arm_strd_base"
>+ [(set (match_operand:SI 0 "arm_hard_register_operand" "+rk")
>+ (plus:SI (match_dup 0)
>+ (const_int -8)))
>+ (set (mem:SI (match_dup 0))
>+ (match_operand:SI 1 "arm_hard_register_operand" "r"))
>+ (set (mem:SI (plus:SI (match_dup 0)
>+ (const_int 4)))
>+ (match_operand:SI 2 "arm_hard_register_operand" "r"))]
>+ "(TARGET_ARM && current_tune->prefer_ldrd_strd
>+ && (!bad_reg_pair_for_arm_ldrd_strd (operands[1], operands[2]))
>+ && (REGNO (operands[1]) != REGNO (operands[0]))
>+ && (REGNO (operands[2]) != REGNO (operands[0])))"
>+ "str%(d%)\t%1, %2, [%0, #-8]!"
>+ [(set_attr "type" "store2")
>+ (set_attr "predicable" "yes")])
Hmmm the question remains if we want to put these into ldmstm.md since
it was theoretically
auto-generated from ldmstm.ml. If this has to be marked to be separate
then I'd like
to regenerate ldmstm.md from ldmstm.ml and differentiate between the
bits that can be auto-generated
and the bits that have been added since.
Otherwise OK.
Ramana
