Hi!
I've tested make check-gcc
RUNTESTFLAGS='--target_board=unix\{-m32/-masm=intel,-m64/-masm=intel\} i386.exp
vect.exp'
testing and looked solely at assembly Error: (there are many scan-assembler*
directives that just fail, and some tests use e.g. only att inline asm
etc.).
The following patch fixes what I found that way. Bootstrapped/regtested on
x86_64-linux and i686-linux, ok for trunk?
The patch fixes:
-FAIL: gcc.target/i386/avx5124vnniw-vp4dpwssd-2.c (test for excess errors)
-FAIL: gcc.target/i386/avx5124vnniw-vp4dpwssds-2.c (test for excess errors)
-FAIL: gcc.target/i386/avx512dq-vreducesd-2.c (test for excess errors)
-FAIL: gcc.target/i386/avx512dq-vreducess-2.c (test for excess errors)
-FAIL: gcc.target/i386/avx512f-vcvtsd2usi-2.c (test for excess errors)
-FAIL: gcc.target/i386/avx512f-vcvtsd2usi64-2.c (test for excess errors)
-FAIL: gcc.target/i386/avx512f-vcvtss2usi-2.c (test for excess errors)
-FAIL: gcc.target/i386/avx512f-vcvtss2usi64-2.c (test for excess errors)
-FAIL: gcc.target/i386/avx512f-vfixupimmsd-2.c (test for excess errors)
-FAIL: gcc.target/i386/avx512f-vfixupimmss-2.c (test for excess errors)
-FAIL: gcc.target/i386/avx512f-vrndscaless-2.c (test for excess errors)
-FAIL: gcc.target/i386/avx512vl-vcvtudq2pd-2.c (test for excess errors)
-FAIL: gcc.target/i386/avx512vl-vpmovswb-2.c (test for excess errors)
-FAIL: gcc.target/i386/avx512vl-vpmovuswb-2.c (test for excess errors)
-FAIL: gcc.target/i386/avx512vl-vpmovwb-2.c (test for excess errors)
-FAIL: gcc.target/i386/avx512vl-vshufpd-2.c (test for excess errors)
BTW, -masm=intel seems to be in quite bad shape even in the assembler, in
various testcases I'm getting errors like on the following reduced one:
int k1, xmm0;
int foo (void) { return k1; }
int bar (void) { return xmm0; }
gcc -masm=intel -O2
/tmp/cch0mo1K.s: Assembler messages:
/tmp/cch0mo1K.s:10: Error: invalid use of register
/tmp/cch0mo1K.s:21: Error: invalid use of register
As ICC generates the same assembly on the instructions:
mov eax, DWORD PTR k1[rip]
...
mov eax, DWORD PTR xmm0[rip]
I think either the intel syntax spec is faulty, or gas is buggy and should
figure out that after *WORD PTR and before [ there is symbol rather than
register name. Some testcases e.g. have k1 as function name and that
results in other asm errors (about .size directive).
2018-04-09 Jakub Jelinek <ja...@redhat.com>
PR target/85281
* config/i386/sse.md (reduces<mode><mask_scalar_name>,
avx512f_vmcmp<mode>3<round_saeonly_name>,
avx512f_vmcmp<mode>3_mask<round_saeonly_name>,
avx512f_sgetexp<mode><mask_scalar_name><round_saeonly_scalar_name>,
avx512f_rndscale<mode><round_saeonly_name>,
avx512dq_ranges<mode><mask_scalar_name><round_saeonly_scalar_name>,
avx512f_vgetmant<mode><mask_scalar_name><round_saeonly_scalar_name>):
Use %<iptr>2 instead of %2 for -masm=intel.
(avx512f_vcvtss2usi<round_name>, avx512f_vcvtss2usiq<round_name>,
avx512f_vcvttss2usi<round_saeonly_name>,
avx512f_vcvttss2usiq<round_saeonly_name>): Use %k1 instead of %1 for
-masm=intel.
(avx512f_vcvtsd2usi<round_name>, avx512f_vcvtsd2usiq<round_name>,
avx512f_vcvttsd2usi<round_saeonly_name>,
avx512f_vcvttsd2usiq<round_saeonly_name>, ufloatv2siv2df2<mask_name>):
Use %q1 instead of %1 for -masm=intel.
(avx512f_sfixupimm<mode><sd_maskz_name><round_saeonly_name>,
avx512f_sfixupimm<mode>_mask<round_saeonly_name>): Use %<iptr>3 instead
of %3 for -masm=intel.
(sse2_shufpd_v2df_mask): Fix a typo, change %{6%} to %{%6%} for
-masm=intel.
(*avx512vl_<code>v2div2qi2_store): Use %w0 instead of %0 for
-masm=intel.
(*avx512vl_<code><mode>v4qi2_store): Use %k0 instead of %0 for
-masm=intel.
(avx512vl_<code><mode>v4qi2_mask_store): Use a single pattern with
%k0 and %1 for -masm=intel rather than two patterns, one with %0 and
%g1.
(*avx512vl_<code><mode>v8qi2_store): Use %q0 instead of %0 for
-masm=intel.
(avx512vl_<code><mode>v8qi2_mask_store): Use a single pattern with
%q0 and %1 for -masm=intel rather than two patterns, one with %0 and
%g1 and one with %0 and %1.
(avx512er_vmrcp28<mode><round_saeonly_name>,
avx512er_vmrsqrt28<mode><round_saeonly_name>): Use %<iptr>1 instead of
%1 for -masm=intel.
(avx5124fmaddps_4fmaddps_mask, avx5124fmaddps_4fmaddss_mask,
avx5124fmaddps_4fnmaddps_mask, avx5124fmaddps_4fnmaddss_mask,
avx5124vnniw_vp4dpwssd_mask, avx5124vnniw_vp4dpwssds_mask): Swap order
of %0 and %{%4%} for -masm=intel.
(avx5124fmaddps_4fmaddps_maskz, avx5124fmaddps_4fmaddss_maskz,
avx5124fmaddps_4fnmaddps_maskz, avx5124fmaddps_4fnmaddss_maskz,
avx5124vnniw_vp4dpwssd_maskz, avx5124vnniw_vp4dpwssds_maskz): Swap
order of %0 and %{%5%}%{z%} for -masm=intel.
--- gcc/config/i386/sse.md.jj 2018-04-09 12:05:38.044703296 +0200
+++ gcc/config/i386/sse.md 2018-04-09 15:15:50.033414875 +0200
@@ -2628,7 +2628,7 @@ (define_insn "reduces<mode><mask_scalar_
(match_dup 1)
(const_int 1)))]
"TARGET_AVX512DQ"
- "vreduce<ssescalarmodesuffix>\t{%3, %2, %1,
%0<mask_scalar_operand4>|%0<mask_scalar_operand4>, %1, %2, %3}"
+ "vreduce<ssescalarmodesuffix>\t{%3, %2, %1,
%0<mask_scalar_operand4>|%0<mask_scalar_operand4>, %1, %<iptr>2, %3}"
[(set_attr "type" "sse")
(set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
@@ -2796,7 +2796,7 @@ (define_insn "avx512f_vmcmp<mode>3<round
UNSPEC_PCMP)
(const_int 1)))]
"TARGET_AVX512F"
- "vcmp<ssescalarmodesuffix>\t{%3, <round_saeonly_op4>%2, %1, %0|%0, %1,
%2<round_saeonly_op4>, %3}"
+ "vcmp<ssescalarmodesuffix>\t{%3, <round_saeonly_op4>%2, %1, %0|%0, %1,
%<iptr>2<round_saeonly_op4>, %3}"
[(set_attr "type" "ssecmp")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
@@ -2814,7 +2814,7 @@ (define_insn "avx512f_vmcmp<mode>3_mask<
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")
(const_int 1))))]
"TARGET_AVX512F"
- "vcmp<ssescalarmodesuffix>\t{%3, <round_saeonly_op5>%2, %1,
%0%{%4%}|%0%{%4%}, %1, %2<round_saeonly_op5>, %3}"
+ "vcmp<ssescalarmodesuffix>\t{%3, <round_saeonly_op5>%2, %1,
%0%{%4%}|%0%{%4%}, %1, %<iptr>2<round_saeonly_op5>, %3}"
[(set_attr "type" "ssecmp")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
@@ -4805,7 +4805,7 @@ (define_insn "avx512f_vcvtss2usi<round_n
(parallel [(const_int 0)]))]
UNSPEC_UNSIGNED_FIX_NOTRUNC))]
"TARGET_AVX512F"
- "vcvtss2usi\t{<round_op2>%1, %0|%0, %1<round_op2>}"
+ "vcvtss2usi\t{<round_op2>%1, %0|%0, %k1<round_op2>}"
[(set_attr "type" "sseicvt")
(set_attr "prefix" "evex")
(set_attr "mode" "SI")])
@@ -4818,7 +4818,7 @@ (define_insn "avx512f_vcvtss2usiq<round_
(parallel [(const_int 0)]))]
UNSPEC_UNSIGNED_FIX_NOTRUNC))]
"TARGET_AVX512F && TARGET_64BIT"
- "vcvtss2usi\t{<round_op2>%1, %0|%0, %1<round_op2>}"
+ "vcvtss2usi\t{<round_op2>%1, %0|%0, %k1<round_op2>}"
[(set_attr "type" "sseicvt")
(set_attr "prefix" "evex")
(set_attr "mode" "DI")])
@@ -4830,7 +4830,7 @@ (define_insn "avx512f_vcvttss2usi<round_
(match_operand:V4SF 1 "<round_saeonly_nimm_scalar_predicate>"
"<round_saeonly_constraint>")
(parallel [(const_int 0)]))))]
"TARGET_AVX512F"
- "vcvttss2usi\t{<round_saeonly_op2>%1, %0|%0, %1<round_saeonly_op2>}"
+ "vcvttss2usi\t{<round_saeonly_op2>%1, %0|%0, %k1<round_saeonly_op2>}"
[(set_attr "type" "sseicvt")
(set_attr "prefix" "evex")
(set_attr "mode" "SI")])
@@ -4842,7 +4842,7 @@ (define_insn "avx512f_vcvttss2usiq<round
(match_operand:V4SF 1 "<round_saeonly_nimm_scalar_predicate>"
"<round_saeonly_constraint>")
(parallel [(const_int 0)]))))]
"TARGET_AVX512F && TARGET_64BIT"
- "vcvttss2usi\t{<round_saeonly_op2>%1, %0|%0, %1<round_saeonly_op2>}"
+ "vcvttss2usi\t{<round_saeonly_op2>%1, %0|%0, %k1<round_saeonly_op2>}"
[(set_attr "type" "sseicvt")
(set_attr "prefix" "evex")
(set_attr "mode" "DI")])
@@ -4855,7 +4855,7 @@ (define_insn "avx512f_vcvtsd2usi<round_n
(parallel [(const_int 0)]))]
UNSPEC_UNSIGNED_FIX_NOTRUNC))]
"TARGET_AVX512F"
- "vcvtsd2usi\t{<round_op2>%1, %0|%0, %1<round_op2>}"
+ "vcvtsd2usi\t{<round_op2>%1, %0|%0, %q1<round_op2>}"
[(set_attr "type" "sseicvt")
(set_attr "prefix" "evex")
(set_attr "mode" "SI")])
@@ -4868,7 +4868,7 @@ (define_insn "avx512f_vcvtsd2usiq<round_
(parallel [(const_int 0)]))]
UNSPEC_UNSIGNED_FIX_NOTRUNC))]
"TARGET_AVX512F && TARGET_64BIT"
- "vcvtsd2usi\t{<round_op2>%1, %0|%0, %1<round_op2>}"
+ "vcvtsd2usi\t{<round_op2>%1, %0|%0, %q1<round_op2>}"
[(set_attr "type" "sseicvt")
(set_attr "prefix" "evex")
(set_attr "mode" "DI")])
@@ -4880,7 +4880,7 @@ (define_insn "avx512f_vcvttsd2usi<round_
(match_operand:V2DF 1 "<round_saeonly_nimm_scalar_predicate>"
"<round_saeonly_constraint>")
(parallel [(const_int 0)]))))]
"TARGET_AVX512F"
- "vcvttsd2usi\t{<round_saeonly_op2>%1, %0|%0, %1<round_saeonly_op2>}"
+ "vcvttsd2usi\t{<round_saeonly_op2>%1, %0|%0, %q1<round_saeonly_op2>}"
[(set_attr "type" "sseicvt")
(set_attr "prefix" "evex")
(set_attr "mode" "SI")])
@@ -4892,7 +4892,7 @@ (define_insn "avx512f_vcvttsd2usiq<round
(match_operand:V2DF 1 "<round_saeonly_nimm_scalar_predicate>"
"<round_saeonly_constraint>")
(parallel [(const_int 0)]))))]
"TARGET_AVX512F && TARGET_64BIT"
- "vcvttsd2usi\t{<round_saeonly_op2>%1, %0|%0, %1<round_saeonly_op2>}"
+ "vcvttsd2usi\t{<round_saeonly_op2>%1, %0|%0, %q1<round_saeonly_op2>}"
[(set_attr "type" "sseicvt")
(set_attr "prefix" "evex")
(set_attr "mode" "DI")])
@@ -5099,7 +5099,7 @@ (define_insn "ufloatv2siv2df2<mask_name>
(match_operand:V4SI 1 "nonimmediate_operand" "vm")
(parallel [(const_int 0) (const_int 1)]))))]
"TARGET_AVX512VL"
- "vcvtudq2pd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
+ "vcvtudq2pd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
(set_attr "mode" "V2DF")])
@@ -8432,7 +8432,7 @@ (define_insn "avx512f_sgetexp<mode><mask
(match_dup 1)
(const_int 1)))]
"TARGET_AVX512F"
- "vgetexp<ssescalarmodesuffix>\t{<round_saeonly_scalar_mask_op3>%2, %1,
%0<mask_scalar_operand3>|%0<mask_scalar_operand3>, %1,
%2<round_saeonly_scalar_mask_op3>}";
+ "vgetexp<ssescalarmodesuffix>\t{<round_saeonly_scalar_mask_op3>%2, %1,
%0<mask_scalar_operand3>|%0<mask_scalar_operand3>, %1,
%<iptr>2<round_saeonly_scalar_mask_op3>}";
[(set_attr "prefix" "evex")
(set_attr "mode" "<ssescalarmode>")])
@@ -8552,7 +8552,7 @@ (define_insn "avx512f_sfixupimm<mode><sd
(match_dup 1)
(const_int 1)))]
"TARGET_AVX512F"
- "vfixupimm<ssescalarmodesuffix>\t{%4, <round_saeonly_sd_mask_op5>%3, %2,
%0<sd_mask_op5>|%0<sd_mask_op5>, %2, %3<round_saeonly_sd_mask_op5>, %4}";
+ "vfixupimm<ssescalarmodesuffix>\t{%4, <round_saeonly_sd_mask_op5>%3, %2,
%0<sd_mask_op5>|%0<sd_mask_op5>, %2, %<iptr>3<round_saeonly_sd_mask_op5>, %4}";
[(set_attr "prefix" "evex")
(set_attr "mode" "<ssescalarmode>")])
@@ -8571,7 +8571,7 @@ (define_insn "avx512f_sfixupimm<mode>_ma
(match_dup 1)
(match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
"TARGET_AVX512F"
- "vfixupimm<ssescalarmodesuffix>\t{%4, <round_saeonly_op6>%3, %2,
%0%{%5%}|%0%{%5%}, %2, %3<round_saeonly_op6>, %4}";
+ "vfixupimm<ssescalarmodesuffix>\t{%4, <round_saeonly_op6>%3, %2,
%0%{%5%}|%0%{%5%}, %2, %<iptr>3<round_saeonly_op6>, %4}";
[(set_attr "prefix" "evex")
(set_attr "mode" "<ssescalarmode>")])
@@ -8598,7 +8598,7 @@ (define_insn "avx512f_rndscale<mode><rou
(match_dup 1)
(const_int 1)))]
"TARGET_AVX512F"
- "vrndscale<ssescalarmodesuffix>\t{%3, <round_saeonly_op4>%2, %1, %0|%0, %1,
%2<round_saeonly_op4>, %3}"
+ "vrndscale<ssescalarmodesuffix>\t{%3, <round_saeonly_op4>%2, %1, %0|%0, %1,
%<iptr>2<round_saeonly_op4>, %3}"
[(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
@@ -8789,7 +8789,7 @@ (define_insn "sse2_shufpd_v2df_mask"
mask |= (INTVAL (operands[4]) - 2) << 1;
operands[3] = GEN_INT (mask);
- return "vshufpd\t{%3, %2, %1, %0%{%6%}%N5|%0%{6%}%N5, %1, %2, %3}";
+ return "vshufpd\t{%3, %2, %1, %0%{%6%}%N5|%0%{%6%}%N5, %1, %2, %3}";
}
[(set_attr "type" "sseshuf")
(set_attr "length_immediate" "1")
@@ -9442,7 +9442,7 @@ (define_insn "*avx512vl_<code>v2div2qi2_
(const_int 12) (const_int 13)
(const_int 14) (const_int 15)]))))]
"TARGET_AVX512VL"
- "vpmov<trunsuffix>qb\t{%1, %0|%0, %1}"
+ "vpmov<trunsuffix>qb\t{%1, %0|%w0, %1}"
[(set_attr "type" "ssemov")
(set_attr "memory" "store")
(set_attr "prefix" "evex")
@@ -9532,7 +9532,7 @@ (define_insn "*avx512vl_<code><mode>v4qi
(const_int 12) (const_int 13)
(const_int 14) (const_int 15)]))))]
"TARGET_AVX512VL"
- "vpmov<trunsuffix><pmov_suff_3>\t{%1, %0|%0, %1}"
+ "vpmov<trunsuffix><pmov_suff_3>\t{%1, %0|%k0, %1}"
[(set_attr "type" "ssemov")
(set_attr "memory" "store")
(set_attr "prefix" "evex")
@@ -9602,11 +9602,7 @@ (define_insn "avx512vl_<code><mode>v4qi2
(const_int 12) (const_int 13)
(const_int 14) (const_int 15)]))))]
"TARGET_AVX512VL"
-{
- if (GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) == 8)
- return "vpmov<trunsuffix><pmov_suff_3>\t{%1, %0%{%2%}|%k0%{%2%}, %1}";
- return "vpmov<trunsuffix><pmov_suff_3>\t{%1, %0%{%2%}|%0%{%2%}, %g1}";
-}
+ "vpmov<trunsuffix><pmov_suff_3>\t{%1, %0%{%2%}|%k0%{%2%}, %1}"
[(set_attr "type" "ssemov")
(set_attr "memory" "store")
(set_attr "prefix" "evex")
@@ -9627,7 +9623,7 @@ (define_insn "*avx512vl_<code><mode>v8qi
(const_int 12) (const_int 13)
(const_int 14) (const_int 15)]))))]
"TARGET_AVX512VL"
- "vpmov<trunsuffix><pmov_suff_3>\t{%1, %0|%0, %1}"
+ "vpmov<trunsuffix><pmov_suff_3>\t{%1, %0|%q0, %1}"
[(set_attr "type" "ssemov")
(set_attr "memory" "store")
(set_attr "prefix" "evex")
@@ -9697,11 +9693,7 @@ (define_insn "avx512vl_<code><mode>v8qi2
(const_int 12) (const_int 13)
(const_int 14) (const_int 15)]))))]
"TARGET_AVX512VL"
-{
- if (GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) == 4)
- return "vpmov<trunsuffix><pmov_suff_3>\t{%1, %0%{%2%}|%0%{%2%}, %g1}";
- return "vpmov<trunsuffix><pmov_suff_3>\t{%1, %0%{%2%}|%0%{%2%}, %1}";
-}
+ "vpmov<trunsuffix><pmov_suff_3>\t{%1, %0%{%2%}|%q0%{%2%}, %1}"
[(set_attr "type" "ssemov")
(set_attr "memory" "store")
(set_attr "prefix" "evex")
@@ -16354,7 +16346,7 @@ (define_insn "avx512er_vmrcp28<mode><rou
(match_operand:VF_128 2 "register_operand" "v")
(const_int 1)))]
"TARGET_AVX512ER"
- "vrcp28<ssescalarmodesuffix>\t{<round_saeonly_op3>%1, %2, %0|%0, %2,
%1<round_saeonly_op3>}"
+ "vrcp28<ssescalarmodesuffix>\t{<round_saeonly_op3>%1, %2, %0|%0, %2,
%<iptr>1<round_saeonly_op3>}"
[(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
(set_attr "type" "sse")
@@ -16380,7 +16372,7 @@ (define_insn "avx512er_vmrsqrt28<mode><r
(match_operand:VF_128 2 "register_operand" "v")
(const_int 1)))]
"TARGET_AVX512ER"
- "vrsqrt28<ssescalarmodesuffix>\t{<round_saeonly_op3>%1, %2, %0|%0, %2,
%1<round_saeonly_op3>}"
+ "vrsqrt28<ssescalarmodesuffix>\t{<round_saeonly_op3>%1, %2, %0|%0, %2,
%<iptr>1<round_saeonly_op3>}"
[(set_attr "length_immediate" "1")
(set_attr "type" "sse")
(set_attr "prefix" "evex")
@@ -19523,7 +19515,7 @@ (define_insn "avx512dq_ranges<mode><mask
(match_dup 1)
(const_int 1)))]
"TARGET_AVX512DQ"
- "vrange<ssescalarmodesuffix>\t{%3, <round_saeonly_scalar_mask_op4>%2, %1,
%0<mask_scalar_operand4>|%0<mask_scalar_operand4>, %1,
%2<round_saeonly_scalar_mask_op4>, %3}"
+ "vrange<ssescalarmodesuffix>\t{%3, <round_saeonly_scalar_mask_op4>%2, %1,
%0<mask_scalar_operand4>|%0<mask_scalar_operand4>, %1,
%<iptr>2<round_saeonly_scalar_mask_op4>, %3}"
[(set_attr "type" "sse")
(set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
@@ -19578,7 +19570,7 @@ (define_insn "avx512f_vgetmant<mode><mas
(match_dup 1)
(const_int 1)))]
"TARGET_AVX512F"
- "vgetmant<ssescalarmodesuffix>\t{%3, <round_saeonly_scalar_mask_op4>%2, %1,
%0<mask_scalar_operand4>|%0<mask_scalar_operand4>, %1,
%2<round_saeonly_scalar_mask_op4>, %3}";
+ "vgetmant<ssescalarmodesuffix>\t{%3, <round_saeonly_scalar_mask_op4>%2, %1,
%0<mask_scalar_operand4>|%0<mask_scalar_operand4>, %1,
%<iptr>2<round_saeonly_scalar_mask_op4>, %3}";
[(set_attr "prefix" "evex")
(set_attr "mode" "<ssescalarmode>")])
@@ -19870,7 +19862,7 @@ (define_insn "avx5124fmaddps_4fmaddps_ma
(match_operand:V16SF 3 "register_operand" "0")
(match_operand:HI 4 "register_operand" "Yk")))]
"TARGET_AVX5124FMAPS"
- "v4fmaddps\t{%2, %g1, %0%{%4%}|%{%4%}%0, %g1, %2}"
+ "v4fmaddps\t{%2, %g1, %0%{%4%}|%0%{%4%}, %g1, %2}"
[(set_attr ("type") ("ssemuladd"))
(set_attr ("prefix") ("evex"))
(set_attr ("mode") ("V16SF"))])
@@ -19885,7 +19877,7 @@ (define_insn "avx5124fmaddps_4fmaddps_ma
(match_operand:V16SF 4 "const0_operand" "C")
(match_operand:HI 5 "register_operand" "Yk")))]
"TARGET_AVX5124FMAPS"
- "v4fmaddps\t{%3, %g2, %0%{%5%}%{z%}|%{%5%}%{z%}%0, %g2, %3}"
+ "v4fmaddps\t{%3, %g2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %g2, %3}"
[(set_attr ("type") ("ssemuladd"))
(set_attr ("prefix") ("evex"))
(set_attr ("mode") ("V16SF"))])
@@ -19911,7 +19903,7 @@ (define_insn "avx5124fmaddps_4fmaddss_ma
(match_operand:V4SF 3 "register_operand" "0")
(match_operand:QI 4 "register_operand" "Yk")))]
"TARGET_AVX5124FMAPS"
- "v4fmaddss\t{%2, %x1, %0%{%4%}|%{%4%}%0, %x1, %2}"
+ "v4fmaddss\t{%2, %x1, %0%{%4%}|%0%{%4%}, %x1, %2}"
[(set_attr ("type") ("ssemuladd"))
(set_attr ("prefix") ("evex"))
(set_attr ("mode") ("SF"))])
@@ -19926,7 +19918,7 @@ (define_insn "avx5124fmaddps_4fmaddss_ma
(match_operand:V4SF 4 "const0_operand" "C")
(match_operand:QI 5 "register_operand" "Yk")))]
"TARGET_AVX5124FMAPS"
- "v4fmaddss\t{%3, %x2, %0%{%5%}%{z%}|%{%5%}%{z%}%0, %x2, %3}"
+ "v4fmaddss\t{%3, %x2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %x2, %3}"
[(set_attr ("type") ("ssemuladd"))
(set_attr ("prefix") ("evex"))
(set_attr ("mode") ("SF"))])
@@ -19952,7 +19944,7 @@ (define_insn "avx5124fmaddps_4fnmaddps_m
(match_operand:V16SF 3 "register_operand" "0")
(match_operand:HI 4 "register_operand" "Yk")))]
"TARGET_AVX5124FMAPS"
- "v4fnmaddps\t{%2, %g1, %0%{%4%}|%{%4%}%0, %g1, %2}"
+ "v4fnmaddps\t{%2, %g1, %0%{%4%}|%0%{%4%}, %g1, %2}"
[(set_attr ("type") ("ssemuladd"))
(set_attr ("prefix") ("evex"))
(set_attr ("mode") ("V16SF"))])
@@ -19967,7 +19959,7 @@ (define_insn "avx5124fmaddps_4fnmaddps_m
(match_operand:V16SF 4 "const0_operand" "C")
(match_operand:HI 5 "register_operand" "Yk")))]
"TARGET_AVX5124FMAPS"
- "v4fnmaddps\t{%3, %g2, %0%{%5%}%{z%}|%{%5%}%{z%}%0, %g2, %3}"
+ "v4fnmaddps\t{%3, %g2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %g2, %3}"
[(set_attr ("type") ("ssemuladd"))
(set_attr ("prefix") ("evex"))
(set_attr ("mode") ("V16SF"))])
@@ -19993,7 +19985,7 @@ (define_insn "avx5124fmaddps_4fnmaddss_m
(match_operand:V4SF 3 "register_operand" "0")
(match_operand:QI 4 "register_operand" "Yk")))]
"TARGET_AVX5124FMAPS"
- "v4fnmaddss\t{%2, %x1, %0%{%4%}|%{%4%}%0, %x1, %2}"
+ "v4fnmaddss\t{%2, %x1, %0%{%4%}|%0%{%4%}, %x1, %2}"
[(set_attr ("type") ("ssemuladd"))
(set_attr ("prefix") ("evex"))
(set_attr ("mode") ("SF"))])
@@ -20008,7 +20000,7 @@ (define_insn "avx5124fmaddps_4fnmaddss_m
(match_operand:V4SF 4 "const0_operand" "C")
(match_operand:QI 5 "register_operand" "Yk")))]
"TARGET_AVX5124FMAPS"
- "v4fnmaddss\t{%3, %x2, %0%{%5%}%{z%}|%{%5%}%{z%}%0, %x2, %3}"
+ "v4fnmaddss\t{%3, %x2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %x2, %3}"
[(set_attr ("type") ("ssemuladd"))
(set_attr ("prefix") ("evex"))
(set_attr ("mode") ("SF"))])
@@ -20034,7 +20026,7 @@ (define_insn "avx5124vnniw_vp4dpwssd_mas
(match_operand:V16SI 3 "register_operand" "0")
(match_operand:HI 4 "register_operand" "Yk")))]
"TARGET_AVX5124VNNIW"
- "vp4dpwssd\t{%2, %g1, %0%{%4%}|%{%4%}%0, %g1, %2}"
+ "vp4dpwssd\t{%2, %g1, %0%{%4%}|%0%{%4%}, %g1, %2}"
[(set_attr ("type") ("ssemuladd"))
(set_attr ("prefix") ("evex"))
(set_attr ("mode") ("TI"))])
@@ -20049,7 +20041,7 @@ (define_insn "avx5124vnniw_vp4dpwssd_mas
(match_operand:V16SI 4 "const0_operand" "C")
(match_operand:HI 5 "register_operand" "Yk")))]
"TARGET_AVX5124VNNIW"
- "vp4dpwssd\t{%3, %g2, %0%{%5%}%{z%}|%{%5%}%{z%}%0, %g2, %3}"
+ "vp4dpwssd\t{%3, %g2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %g2, %3}"
[(set_attr ("type") ("ssemuladd"))
(set_attr ("prefix") ("evex"))
(set_attr ("mode") ("TI"))])
@@ -20075,7 +20067,7 @@ (define_insn "avx5124vnniw_vp4dpwssds_ma
(match_operand:V16SI 3 "register_operand" "0")
(match_operand:HI 4 "register_operand" "Yk")))]
"TARGET_AVX5124VNNIW"
- "vp4dpwssds\t{%2, %g1, %0%{%4%}|%{%4%}%0, %g1, %2}"
+ "vp4dpwssds\t{%2, %g1, %0%{%4%}|%0%{%4%}, %g1, %2}"
[(set_attr ("type") ("ssemuladd"))
(set_attr ("prefix") ("evex"))
(set_attr ("mode") ("TI"))])
@@ -20090,7 +20082,7 @@ (define_insn "avx5124vnniw_vp4dpwssds_ma
(match_operand:V16SI 4 "const0_operand" "C")
(match_operand:HI 5 "register_operand" "Yk")))]
"TARGET_AVX5124VNNIW"
- "vp4dpwssds\t{%3, %g2, %0%{%5%}%{z%}|%{%5%}%{z%}%0, %g2, %3}"
+ "vp4dpwssds\t{%3, %g2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %g2, %3}"
[(set_attr ("type") ("ssemuladd"))
(set_attr ("prefix") ("evex"))
(set_attr ("mode") ("TI"))])
Jakub
