Some of the carryin insn patterns are missing a register constraint.
That means that the register allocator can pick practically anything
to hold that value, including memory locations, or registers of the
wrong class.
PR target/86887
* config/aarch64/aarch64.md (add<mode>3_carryinC_zero): Add missing
register constraint to operand 0.
(add<mode>3_carryinC): Likewise.
(add<mode>3_carryinV_zero, add<mode>3_carryinV): Likewise.
R.
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 955bf18..a73ecc7 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -2429,7 +2429,7 @@ (define_insn "*add<mode>3_carryinC_zero"
(plus:GPI
(match_operand:GPI 3 "aarch64_carry_operation" "")
(match_dup 1)))))
- (set (match_operand:GPI 0 "register_operand")
+ (set (match_operand:GPI 0 "register_operand" "=r")
(plus:GPI (match_dup 3) (match_dup 1)))]
""
"adcs\\t%<w>0, %<w>1, <w>zr"
@@ -2450,7 +2450,7 @@ (define_insn "*add<mode>3_carryinC"
(match_operand:GPI 4 "aarch64_carry_operation" "")
(match_dup 1))
(match_dup 2)))))
- (set (match_operand:GPI 0 "register_operand")
+ (set (match_operand:GPI 0 "register_operand" "=r")
(plus:GPI
(plus:GPI (match_dup 4) (match_dup 1))
(match_dup 2)))]
@@ -2495,7 +2495,7 @@ (define_insn "*add<mode>3_carryinV_zero"
(plus:GPI
(match_operand:GPI 3 "aarch64_carry_operation" "")
(match_dup 1)))))
- (set (match_operand:GPI 0 "register_operand")
+ (set (match_operand:GPI 0 "register_operand" "=r")
(plus:GPI (match_dup 3) (match_dup 1)))]
""
"adcs\\t%<w>0, %<w>1, <w>zr"
@@ -2516,7 +2516,7 @@ (define_insn "*add<mode>3_carryinV"
(match_operand:GPI 4 "aarch64_carry_operation" "")
(match_dup 1))
(match_dup 2)))))
- (set (match_operand:GPI 0 "register_operand")
+ (set (match_operand:GPI 0 "register_operand" "=r")
(plus:GPI
(plus:GPI (match_dup 4) (match_dup 1))
(match_dup 2)))]
