Hi Peter,

Is there any update on this issues?
arm-none-linux-gnueabihf native toolchain has been mis-compiled for a while.

I got the following dump from the test case.

x1 is an early clobber operand in the inline assembly statement,
r92 should conflict with x1?

;; a0(r93,l0) conflicts: a1(r92,l0)
;;     total conflict hard regs: 0-4 16 17 30
;;     conflict hard regs: 0-4 16 17 30


;; a1(r92,l0) conflicts: a0(r93,l0)
;;     total conflict hard regs: 0 2-4 16 17 30
;;     conflict hard regs: 0 2-4 16 17 30

Dump from ira.

(insn 2 8 6 2 (set (reg/v:DI 92 [ arg ])
        (reg:DI 97)) "test.c":3:1 47 {*movdi_aarch64}
     (expr_list:REG_DEAD (reg:DI 97)
        (nil)))
(insn 7 6 9 2 (set (reg/v:DI 1 x1 [ x1 ])
        (reg/v:DI 92 [ arg ])) "test.c":13:26 47 {*movdi_aarch64}
     (nil))
(insn 11 10 14 2 (set (reg/f:DI 93)
        (const_int 0 [0])) "test.c":17:3 47 {*movdi_aarch64}
     (expr_list:REG_EQUIV (const_int 0 [0])
        (nil)))
(insn 14 11 21 2 (parallel [
            (set (reg/v:DI 0 x0 [ x0 ])
                (asm_operands/v:DI ("      casp    %0, %1, %3, %4, %2
        eor     %0, %0, %6
        eor     %1, %1, %7
        orr     %0, %0, %1
") ("=&r") 0 [
                        (reg/v:DI 2 x2 [ x2 ])
                        (reg/v:DI 3 x3 [ x3 ])
                        (reg/v:DI 4 x4 [ x4 ])
                        (reg/f:DI 93)
                        (reg/v:DI 92 [ arg ])
                        (reg/v:DI 0 x0 [ x0 ])
                        (reg/v:DI 1 x1 [ x1 ])
                        (mem:DI (reg/f:DI 93) [1 MEM[(long unsigned int *)0B]+0 
S8 A128])
                    ]
                     [
                        (asm_input:DI ("r") test.c:17)
                        (asm_input:DI ("r") test.c:17)
                        (asm_input:DI ("r") test.c:17)
                        (asm_input:DI ("r") test.c:17)
                        (asm_input:DI ("r") test.c:17)
                        (asm_input:DI ("0") test.c:17)
                        (asm_input:DI ("1") test.c:17)
                        (asm_input:DI ("Q") test.c:17)
                    ]
                     [] test.c:17))
            (set (reg/v:DI 1 x1 [ x1 ])
                (asm_operands/v:DI ("      casp    %0, %1, %3, %4, %2
        eor     %0, %0, %6
        eor     %1, %1, %7
        orr     %0, %0, %1
") ("=&r") 1 [
                        (reg/v:DI 2 x2 [ x2 ])
                        (reg/v:DI 3 x3 [ x3 ])
                        (reg/v:DI 4 x4 [ x4 ])
                        (reg/f:DI 93)
                        (reg/v:DI 92 [ arg ])
                        (reg/v:DI 0 x0 [ x0 ])
                        (reg/v:DI 1 x1 [ x1 ])
                        (mem:DI (reg/f:DI 93) [1 MEM[(long unsigned int *)0B]+0 
S8 A128])
                    ]
                     [
                        (asm_input:DI ("r") test.c:17)
                        (asm_input:DI ("r") test.c:17)
                        (asm_input:DI ("r") test.c:17)
                        (asm_input:DI ("r") test.c:17)
                        (asm_input:DI ("r") test.c:17)
                        (asm_input:DI ("0") test.c:17)
                        (asm_input:DI ("1") test.c:17)
                        (asm_input:DI ("Q") test.c:17)
                    ]
                     [] test.c:17))
            (set (mem:DI (reg/f:DI 93) [1 MEM[(long unsigned int *)0B]+0 S8 
A128])
                (asm_operands/v:DI ("      casp    %0, %1, %3, %4, %2
        eor     %0, %0, %6
        eor     %1, %1, %7
        orr     %0, %0, %1
") ("=Q") 2 [
                        (reg/v:DI 2 x2 [ x2 ])
                        (reg/v:DI 3 x3 [ x3 ])
                        (reg/v:DI 4 x4 [ x4 ])
                        (reg/f:DI 93)
                        (reg/v:DI 92 [ arg ])
                        (reg/v:DI 0 x0 [ x0 ])
                        (reg/v:DI 1 x1 [ x1 ])
                        (mem:DI (reg/f:DI 93) [1 MEM[(long unsigned int *)0B]+0 
S8 A128])
                    ]
                     [
                        (asm_input:DI ("r") test.c:17)
                        (asm_input:DI ("r") test.c:17)
                        (asm_input:DI ("r") test.c:17)
                        (asm_input:DI ("r") test.c:17)
                        (asm_input:DI ("r") test.c:17)
                        (asm_input:DI ("0") test.c:17)
                        (asm_input:DI ("1") test.c:17)
                        (asm_input:DI ("Q") test.c:17)
                    ]
                     [] test.c:17))
            (clobber (reg:DI 30 x30))
            (clobber (reg:DI 17 x17))
            (clobber (reg:DI 16 x16))
        ]) "test.c":17:3 -1
     (expr_list:REG_DEAD (reg/f:DI 93)
        (expr_list:REG_DEAD (reg/v:DI 92 [ arg ])
            (expr_list:REG_DEAD (reg/v:DI 4 x4 [ x4 ])
                (expr_list:REG_DEAD (reg/v:DI 3 x3 [ x3 ])
                    (expr_list:REG_DEAD (reg/v:DI 2 x2 [ x2 ])
                        (expr_list:REG_UNUSED (reg:DI 30 x30)
                            (expr_list:REG_UNUSED (reg:DI 17 x17)
                                (expr_list:REG_UNUSED (reg:DI 16 x16)
                                    (expr_list:REG_UNUSED (reg/v:DI 1 x1 [ x1 ])
                                        (nil)))))))))))


Regards,
Renlin


On 10/16/2018 03:24 AM, Peter Bergner wrote:
On 10/11/18 10:40 PM, Jeff Law wrote:
On 10/11/18 1:23 PM, Peter Bergner wrote:
        * ira-lives (non_conflicting_reg_copy_p): Disable for non LRA targets.
So this helped the alpha & hppa and sh4.

I'm still seeing failures on the aarch64, s390x.  No surprise on these
since they use LRA by default and would be unaffected by this patch.

Ok, I was able to reduce the aarch64 test case down to the minimum test case
that still kept the kernel's __cmpxchg_double() function intact.  I tested
the patch you're currently running on your builders which changed some
of the "... == OP_OUT" to "... != OP_IN", etc and it doesn't fix the
following test case, like it seems to fix the s390 issue and segher's
small test case (both aarch64 and ppc64).

It's late here, so I'll start digging into this one in the morning.

Peter



bergner@pike:~/gcc/BUGS/PR87507/$ cat slub-min.c
long
__cmpxchg_double (unsigned long arg)
{
   unsigned long old1 = 0;
   unsigned long old2 = arg;
   unsigned long new1 = 0;
   unsigned long new2 = 0;
   volatile void *ptr = 0;

   unsigned long oldval1 = old1;
   unsigned long oldval2 = old2;
   register unsigned long x0 asm ("x0") = old1;
   register unsigned long x1 asm ("x1") = old2;
   register unsigned long x2 asm ("x2") = new1;
   register unsigned long x3 asm ("x3") = new2;
   register unsigned long x4 asm ("x4") = (unsigned long) ptr;
   asm volatile (" casp    %[old1], %[old2], %[new1], %[new2], %[v]\n"
                "  eor     %[old1], %[old1], %[oldval1]\n"
                "  eor     %[old2], %[old2], %[oldval2]\n"
                "  orr     %[old1], %[old1], %[old2]\n"
                : [old1] "+&r" (x0), [old2] "+&r" (x1), [v] "+Q" (* (unsigned 
long *) ptr)
                : [new1] "r" (x2), [new2] "r" (x3), [ptr] "r" (x4), [oldval1] "r" 
(oldval1),[oldval2] "r" (oldval2)
                : "x16", "x17", "x30");
   return x0;
}
bergner@pike:~/gcc/BUGS/PR87507/$ 
/home/bergner/gcc/build/gcc-fsf-mainline-aarch64-r264897/gcc/xgcc 
-B/home/bergner/gcc/build/gcc-fsf-mainline-aarch64-r264897/gcc -O2 
-march=armv8.1-a -c slub-min.c
/tmp/ccQCkiSG.s: Assembler messages:
/tmp/ccQCkiSG.s:24: Error: reg pair must be contiguous at operand 2 -- `casp 
x0,x6,x2,x3,[x5]'



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