Hi All,
This patch adds tests for AArch64 and Arm to test the autovectorization
of complex numbers using the Armv8.3-a instructions.
This patch enables them only for AArch64 at this point.
Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
The instructions have also been tested on aarch64-none-elf on a Armv8.3-a model
and -march=Armv8.3-a+fp16 and all tests pass.
Ok for trunk?
Thanks,
Tamar
gcc/testsuite/ChangeLog:
2018-11-11 Tamar Christina <tamar.christ...@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays-autovec-270.c: New
test.
* gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays-autovec-90.c: New
test.
* gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_2.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_3.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_4.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_5.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_6.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vcadd-complex-autovec.c: New
test.
* gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_2.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_3.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_4.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_5.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_6.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vcmla-complex-autovec.c: New
test.
* gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_180_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_180_2.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_180_3.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_2.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_270_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_270_2.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_270_3.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_3.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90_1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90_2.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90_3.c: New test.
--
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays-autovec-270.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays-autovec-270.c
new file mode 100644
index 0000000000000000000000000000000000000000..8f660f392153c3a6a83b31486e275be316c6ad2b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays-autovec-270.c
@@ -0,0 +1,13 @@
+/* { dg-skip-if "" { *-*-* } } */
+
+#define N 200
+
+__attribute__ ((noinline))
+void calc (TYPE a[N], TYPE b[N], TYPE *c)
+{
+ for (int i=0; i < N; i+=2)
+ {
+ c[i] = a[i] + b[i+1];
+ c[i+1] = a[i+1] - b[i];
+ }
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays-autovec-90.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays-autovec-90.c
new file mode 100644
index 0000000000000000000000000000000000000000..14014b9d4f2c41e75be3e253d2e47e639e4224c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays-autovec-90.c
@@ -0,0 +1,12 @@
+/* { dg-skip-if "" { *-*-* } } */
+#define N 200
+
+__attribute__ ((noinline))
+void calc (TYPE a[N], TYPE b[N], TYPE *c)
+{
+ for (int i=0; i < N; i+=2)
+ {
+ c[i] = a[i] - b[i+1];
+ c[i+1] = a[i+1] + b[i];
+ }
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..627f2e78daee9c4a4f86c2071080b4114820c209
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_1.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_df } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+
+#define TYPE double
+#include "vcadd-arrays-autovec-90.c"
+
+extern void abort(void);
+
+int main()
+{
+ TYPE a[N] = {1.0, 2.0, 3.0, 4.0};
+ TYPE b[N] = {4.0, 2.0, 1.5, 4.5};
+ TYPE c[N] = {0};
+ calc (a, b, c);
+
+ if (c[0] != -1.0 || c[1] != 6.0)
+ abort ();
+
+ if (c[2] != -1.5 || c[3] != 5.5)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.2d, v[0-9]+\.2d, v[0-9]+\.2d, #90} 1 { target { aarch64*-*-* } } } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_2.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..d94becdb69386c08c07f8b763aea3fa050e6644c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_2.c
@@ -0,0 +1,29 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_sf } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+
+#define TYPE float
+#include "vcadd-arrays-autovec-90.c"
+
+extern void abort(void);
+
+int main()
+{
+ TYPE a[N] = {1.0, 2.0, 3.0, 4.0};
+ TYPE b[N] = {4.0, 2.0, 1.5, 4.5};
+ TYPE c[N] = {0};
+ calc (a, b, c);
+
+ if (c[0] != -1.0 || c[1] != 6.0)
+ abort ();
+
+ if (c[2] != -1.5 || c[3] != 5.5)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.4s, v[0-9]+\.4s, v[0-9]+\.4s, #90} 1 { target { aarch64*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_3.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_3.c
new file mode 100644
index 0000000000000000000000000000000000000000..df33c313847ac2f519deb8346c3167b015913299
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_3.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_hf } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -march=armv8.3-a+fp16 -save-temps" } */
+
+#define TYPE _Float16
+#include "vcadd-arrays-autovec-90.c"
+
+extern void abort(void);
+
+int main()
+{
+ TYPE a[N] = {1.0, 2.0, 3.0, 4.0};
+ TYPE b[N] = {4.0, 2.0, 1.5, 4.5};
+ TYPE c[N] = {0};
+ calc (a, b, c);
+
+ if (c[0] != -1.0 || c[1] != 6.0)
+ abort ();
+
+ if (c[2] != -1.5 || c[3] != 5.5)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.8h, v[0-9]+\.8h, v[0-9]+\.8h, #90} 1 { target { aarch64*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_4.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_4.c
new file mode 100644
index 0000000000000000000000000000000000000000..bbd4d004177328023eb6270c7b38cd9ae0357c60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_4.c
@@ -0,0 +1,29 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_df } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+
+#define TYPE double
+#include "vcadd-arrays-autovec-270.c"
+
+extern void abort(void);
+
+int main()
+{
+ TYPE a[N] = {1.0, 2.0, 3.0, 4.0};
+ TYPE b[N] = {4.0, 2.0, 1.5, 4.5};
+ TYPE c[N] = {0};
+ calc (a, b, c);
+
+ if (c[0] != 3.0 || c[1] != -2.0)
+ abort ();
+
+ if (c[2] != 7.5 || c[3] != 2.5)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.2d, v[0-9]+\.2d, v[0-9]+\.2d, #270} 1 { target { aarch64*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_5.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_5.c
new file mode 100644
index 0000000000000000000000000000000000000000..8f719d072af591f624f89ef458c0f1552cb38a15
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_5.c
@@ -0,0 +1,29 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_sf } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+
+#define TYPE float
+#include "vcadd-arrays-autovec-270.c"
+
+extern void abort(void);
+
+int main()
+{
+ TYPE a[N] = {1.0, 2.0, 3.0, 4.0};
+ TYPE b[N] = {4.0, 2.0, 1.5, 4.5};
+ TYPE c[N] = {0};
+ calc (a, b, c);
+
+ if (c[0] != 3.0 || c[1] != -2.0)
+ abort ();
+
+ if (c[2] != 7.5 || c[3] != 2.5)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.4s, v[0-9]+\.4s, v[0-9]+\.4s, #270} 1 { target { aarch64*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_6.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_6.c
new file mode 100644
index 0000000000000000000000000000000000000000..3f665ba31e2e2debaa7b78f9dce907a8f94951e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_6.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_hf } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -march=armv8.3-a+fp16 -save-temps" } */
+
+#define TYPE _Float16
+#include "vcadd-arrays-autovec-270.c"
+
+extern void abort(void);
+
+int main()
+{
+ TYPE a[N] = {1.0, 2.0, 3.0, 4.0};
+ TYPE b[N] = {4.0, 2.0, 1.5, 4.5};
+ TYPE c[N] = {0};
+ calc (a, b, c);
+
+ if (c[0] != 3.0 || c[1] != -2.0)
+ abort ();
+
+ if (c[2] != 7.5 || c[3] != 2.5)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.8h, v[0-9]+\.8h, v[0-9]+\.8h, #270} 1 { target { aarch64*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex-autovec.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex-autovec.c
new file mode 100644
index 0000000000000000000000000000000000000000..2a301e6ec0a9ba23a16c39d9c36ee281422f1803
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex-autovec.c
@@ -0,0 +1,12 @@
+/* { dg-skip-if "" { *-*-* } } */
+
+#include <complex.h>
+
+#define N 200
+
+__attribute__ ((noinline))
+void calc (TYPE complex a[N], TYPE complex b[N], TYPE complex c[N])
+{
+ for (int i=0; i < N; i++)
+ c[i] = a[i] + b[i] ROT;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..a8c596645ccfb60c89942312620c31636c3f3f40
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_1.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_df } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+
+#define TYPE double
+#define ROT * I
+#include "vcadd-complex-autovec.c"
+
+extern void abort(void);
+
+#include <stdio.h>
+
+int main()
+{
+ TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+ TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+ TYPE complex c[N] = {0};
+ calc (a, b, c);
+
+ if (creal (c[0]) != -1.0 || cimag (c[0]) != 6.0)
+ abort ();
+
+ if (creal (c[1]) != -1.5 || cimag (c[1]) != 5.5)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.2d, v[0-9]+\.2d, v[0-9]+\.2d, #90} 1 { target { aarch64*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_2.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..abed2b1e824f010feb959d6491df1b7fcb943d23
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_2.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_sf } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+
+#define TYPE float
+#define ROT * I
+#include "vcadd-complex-autovec.c"
+
+extern void abort(void);
+
+int main()
+{
+ TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+ TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+ TYPE complex c[N] = {0};
+ calc (a, b, c);
+
+ if (creal (c[0]) != -1.0 || cimag (c[0]) != 6.0)
+ abort ();
+
+ if (creal (c[1]) != -1.5 || cimag (c[1]) != 5.5)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.4s, v[0-9]+\.4s, v[0-9]+\.4s, #90} 1 { target { aarch64*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_3.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_3.c
new file mode 100644
index 0000000000000000000000000000000000000000..e097d79f9867be30b59118578b00540b60fe2b2c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_3.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_hf } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -march=armv8.3-a+fp16 -save-temps" } */
+
+#define TYPE _Float16
+#define ROT * I
+#include "vcadd-complex-autovec.c"
+
+extern void abort(void);
+
+int main()
+{
+ TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+ TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+ TYPE complex c[N] = {0};
+ calc (a, b, c);
+
+ if (creal (c[0]) != -1.0 || cimag (c[0]) != 6.0)
+ abort ();
+
+ if (creal (c[1]) != -1.5 || cimag (c[1]) != 5.5)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.8h, v[0-9]+\.8h, v[0-9]+\.8h, #90} 1 { target { aarch64*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_4.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_4.c
new file mode 100644
index 0000000000000000000000000000000000000000..fb4b08bed42452e0a5e9c6315a6317b60c0b5d5d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_4.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_df } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+
+#define TYPE double
+#define ROT * I * I * I
+#include "vcadd-complex-autovec.c"
+
+extern void abort(void);
+
+int main()
+{
+ TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+ TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+ TYPE complex c[N] = {0};
+ calc (a, b, c);
+
+ if (creal (c[0]) != 3.0 || cimag (c[0]) != -2.0)
+ abort ();
+
+ if (creal (c[1]) != 7.5 || cimag (c[1]) != 2.5)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.2d, v[0-9]+\.2d, v[0-9]+\.2d, #270} 1 { target { aarch64*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_5.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_5.c
new file mode 100644
index 0000000000000000000000000000000000000000..71cc559d1d8c1c9ad0a7a8274024f1954cca04af
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_5.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_sf } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+
+#define TYPE float
+#define ROT * I * I * I
+#include "vcadd-complex-autovec.c"
+
+extern void abort(void);
+
+int main()
+{
+ TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+ TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+ TYPE complex c[N] = {0};
+ calc (a, b, c);
+
+ if (creal (c[0]) != 3.0 || cimag (c[0]) != -2.0)
+ abort ();
+
+ if (creal (c[1]) != 7.5 || cimag (c[1]) != 2.5)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.4s, v[0-9]+\.4s, v[0-9]+\.4s, #270} 1 { target { aarch64*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_6.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_6.c
new file mode 100644
index 0000000000000000000000000000000000000000..a964b29622b0e2715268c7a03a894ac48e82e98b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_6.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_hf } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -march=armv8.3-a+fp16 -save-temps" } */
+
+#define TYPE _Float16
+#define ROT * I * I * I
+#include "vcadd-complex-autovec.c"
+
+extern void abort(void);
+
+int main()
+{
+ TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+ TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+ TYPE complex c[N] = {0};
+ calc (a, b, c);
+
+ if (creal (c[0]) != 3.0 || cimag (c[0]) != -2.0)
+ abort ();
+
+ if (creal (c[1]) != 7.5 || cimag (c[1]) != 2.5)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.8h, v[0-9]+\.8h, v[0-9]+\.8h, #270} 1 { target { aarch64*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex-autovec.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex-autovec.c
new file mode 100644
index 0000000000000000000000000000000000000000..1ad7cc319eeef2ea15f530997a9ffc09571ea02e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex-autovec.c
@@ -0,0 +1,11 @@
+/* { dg-skip-if "" { *-*-* } } */
+#include <complex.h>
+
+#define N 200
+
+__attribute__ ((noinline, noipa))
+void calc (TYPE complex a[N], TYPE complex b[N], TYPE complex c[N])
+{
+ for (int i=0; i < N; i++)
+ c[i] += a[i] * b[i] ROT;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..87a2d25e06fa5ab0b59bc8c9ccbf629f533f0e10
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_1.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_df } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+/* { dg-keep-saved-temps ".s" ".o" ".exe" } */
+#define TYPE double
+#define ROT
+#include "vcmla-complex-autovec.c"
+
+extern void abort(void);
+
+#include <stdio.h>
+
+int main()
+{
+ TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+ TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+ TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
+ calc (a, b, c);
+
+ if (creal (c[0]) != 2.5 || cimag (c[0]) != 11.5)
+ abort ();
+
+ if (creal (c[1]) != -11.5 || cimag (c[1]) != 21.0)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+\.2d, v[0-9]+\.2d, v[0-9]+\.2d, #(?:0|90)} 2 { target { aarch64*-*-* } } } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_180_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_180_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..8703902944b3e65e2f3dba659fc9425bea4cdd27
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_180_1.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_df } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+
+#define TYPE double
+#define ROT * I * I
+#include "vcmla-complex-autovec.c"
+
+extern void abort(void);
+
+int main()
+{
+ TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+ TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+ TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
+ calc (a, b, c);
+
+ if (creal (c[0]) != 2.5 || cimag (c[0]) != -8.5)
+ abort ();
+
+ if (creal (c[1]) != 15.5 || cimag (c[1]) != -18.0)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+\.2d, v[0-9]+\.2d, v[0-9]+\.2d, #(?:180|270)} 2 { target { aarch64*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_180_2.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_180_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..10833bde24e24d944f2de068f492ac4505b4c012
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_180_2.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_sf } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+
+#define TYPE float
+#define ROT * I * I
+#include "vcmla-complex-autovec.c"
+
+extern void abort(void);
+
+int main()
+{
+ TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+ TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+ TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
+ calc (a, b, c);
+
+ if (creal (c[0]) != 2.5 || cimag (c[0]) != -8.5)
+ abort ();
+
+ if (creal (c[1]) != 15.5 || cimag (c[1]) != -18.0)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+\.4s, v[0-9]+\.4s, v[0-9]+\.4s, #(?:180|270)} 2 { target { aarch64*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_180_3.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_180_3.c
new file mode 100644
index 0000000000000000000000000000000000000000..2699577fd7b5a4e565dea702d96e91e0beded0f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_180_3.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_hf } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -march=armv8.3-a+fp16 -save-temps" } */
+
+#define TYPE _Float16
+#define ROT * I * I
+#include "vcmla-complex-autovec.c"
+
+extern void abort(void);
+
+int main()
+{
+ TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+ TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+ TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
+ calc (a, b, c);
+
+ if (creal (c[0]) != 2.5 || cimag (c[0]) != -8.5)
+ abort ();
+
+ if (creal (c[1]) != 15.5 || cimag (c[1]) != -18.0)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+\.8h, v[0-9]+\.8h, v[0-9]+\.8h, #(?:180|270)} 2 { target { aarch64*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_2.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..7bdca9ad5033c99ea7035a7e1e0d411b64db1b73
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_2.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_sf } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+
+#define TYPE float
+#define ROT
+#include "vcmla-complex-autovec.c"
+
+extern void abort(void);
+
+int main()
+{
+ TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+ TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+ TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
+ calc (a, b, c);
+
+ if (creal (c[0]) != 2.5 || cimag (c[0]) != 11.5)
+ abort ();
+
+ if (creal (c[1]) != -11.5 || cimag (c[1]) != 21.0)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+\.4s, v[0-9]+\.4s, v[0-9]+\.4s, #(?:0|90)} 2 { target { aarch64*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_270_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_270_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..1c7584d4f949cf448cb1da4219f5dd9db14206cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_270_1.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_df } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+
+#define TYPE double
+#define ROT * I * I * I
+#include "vcmla-complex-autovec.c"
+
+extern void abort(void);
+
+int main()
+{
+ TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+ TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+ TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
+ calc (a, b, c);
+
+ if (creal (c[0]) != 12.5 || cimag (c[0]) != 1.5)
+ abort ();
+
+ if (creal (c[1]) != 21.5 || cimag (c[1]) != 15.0)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-not {fcmla} { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-not {vcmla} { target { arm*-*-* } } } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_270_2.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_270_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..eb5cd4ec760031d0ab81d8dcce224e94c234c764
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_270_2.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_sf } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+
+#define TYPE float
+#define ROT * I * I * I
+#include "vcmla-complex-autovec.c"
+
+extern void abort(void);
+
+int main()
+{
+ TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+ TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+ TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
+ calc (a, b, c);
+
+ if (creal (c[0]) != 12.5 || cimag (c[0]) != 1.5)
+ abort ();
+
+ if (creal (c[1]) != 21.5 || cimag (c[1]) != 15.0)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-not {fcmla} { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-not {vcmla} { target { arm*-*-* } } } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_270_3.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_270_3.c
new file mode 100644
index 0000000000000000000000000000000000000000..8f1585c14cc0637a17d335b93e9198b1549f753d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_270_3.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_hf } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -march=armv8.3-a+fp16 -save-temps" } */
+
+#define TYPE _Float16
+#define ROT * I * I * I
+#include "vcmla-complex-autovec.c"
+
+extern void abort(void);
+
+int main()
+{
+ TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+ TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+ TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
+ calc (a, b, c);
+
+ if (creal (c[0]) != 12.5 || cimag (c[0]) != 1.5)
+ abort ();
+
+ if (creal (c[1]) != 21.5 || cimag (c[1]) != 15.0)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-not {fcmla} { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-not {vcmla} { target { arm*-*-* } } } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_3.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_3.c
new file mode 100644
index 0000000000000000000000000000000000000000..bd8ead4d58884836bbc13005c59804a26d24617e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_3.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_hf } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -march=armv8.3-a+fp16 -save-temps" } */
+
+#define TYPE _Float16
+#define ROT
+#include "vcmla-complex-autovec.c"
+
+extern void abort(void);
+
+int main()
+{
+ TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+ TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+ TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
+ calc (a, b, c);
+
+ if (creal (c[0]) != 2.5 || cimag (c[0]) != 11.5)
+ abort ();
+
+ if (creal (c[1]) != -11.5 || cimag (c[1]) != 21.0)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+\.8h, v[0-9]+\.8h, v[0-9]+\.8h, #(?:0|90)} 2 { target { aarch64*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..fafb8b576b5d3d44ca09c4050be220c2195c0eba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90_1.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_df } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+
+#define TYPE double
+#define ROT * I
+#include "vcmla-complex-autovec.c"
+
+extern void abort(void);
+
+#include <stdio.h>
+
+int main()
+{
+ TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+ TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+ TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
+ calc (a, b, c);
+
+ if (creal (c[0]) != -7.5 || cimag (c[0]) != 1.5)
+ abort ();
+
+ if (creal (c[1]) != -17.5 || cimag (c[1]) != -12.0)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-not {fcmla} { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-not {vcmla} { target { arm*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90_2.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..68d395a6075fb19ad79f4f4d41db41bfa4227931
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90_2.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_sf } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+
+#define TYPE float
+#define ROT * I
+#include "vcmla-complex-autovec.c"
+
+extern void abort(void);
+
+int main()
+{
+ TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+ TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+ TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
+ calc (a, b, c);
+
+ if (creal (c[0]) != -7.5 || cimag (c[0]) != 1.5)
+ abort ();
+
+ if (creal (c[1]) != -17.5 || cimag (c[1]) != -12.0)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-not {fcmla} { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-not {vcmla} { target { arm*-*-* } } } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90_3.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90_3.c
new file mode 100644
index 0000000000000000000000000000000000000000..acb566df44e1ce21a7039ae90af9bba7c8e49c50
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90_3.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_hf } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -march=armv8.3-a+fp16 -save-temps" } */
+
+#define TYPE _Float16
+#define ROT * I
+#include "vcmla-complex-autovec.c"
+
+extern void abort(void);
+
+int main()
+{
+ TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+ TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+ TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
+ calc (a, b, c);
+
+ if (creal (c[0]) != -7.5 || cimag (c[0]) != 1.5)
+ abort ();
+
+ if (creal (c[1]) != -17.5 || cimag (c[1]) != -12.0)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-not {fcmla} { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-not {vcmla} { target { arm*-*-* } } } } */
