Bootstrapped and regtested on s390x-redhat-linux. Fixes rXsbg_mode_sXl test failures.
Combine used to give us (set (reg:SI 65) (ior:SI (lshiftrt:SI (reg:SI 3 %r3 [ bD.2238 ]) (const_int 2 [0x2])) (reg:SI 2 %r2 [ aD.2237 ]))) but now we get (set (reg:SI 65) (ior:SI (subreg:SI (zero_extract:DI (reg:DI 69) (const_int 32 [0x20]) (const_int 30 [0x1e])) 4) (subreg:SI (reg:DI 68) 4))) or (set (reg:SI 65) (ior:SI (subreg:SI (and:DI (lshiftrt:DI (reg:DI 69) (const_int 2 [0x2])) (const_int 4294967295 [0xffffffff])) 4) (subreg:SI (reg:DI 68) 4))) with an extra subreg, which appears because pseudos, unlike hard registers, can be accessed only using their natural mode. This patch adds a special case for that. Also, it performs r*sbg bit index computations during gcc run, so that expectations do not depend on which concrete pattern was matched. gcc/ChangeLog: 2018-11-15 Ilya Leoshkevich <i...@linux.ibm.com> * config/s390/s390.md (*r<noxa>sbg_<mode>_srl_bitmask): Do not delegate arithmetic to assembler. (*r<noxa>sbg_<mode>_sll): Likewise. (*r<noxa>sbg_<mode>_srl): Likewise. (*r<noxa>sbg_sidi_srl): New pattern. * gcc.target/s390/md/rXsbg_mode_sXl.c: Do not use arithmetic in r{o,x}sbg expectations. * gcc.target/s390/risbg-ll-2.c: Likewise. --- gcc/config/s390/s390.md | 42 +++++++++++++++++-- .../gcc.target/s390/md/rXsbg_mode_sXl.c | 16 +++---- gcc/testsuite/gcc.target/s390/risbg-ll-2.c | 2 +- 3 files changed, 48 insertions(+), 12 deletions(-) diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 957c378e34f..7a556d40224 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -4276,7 +4276,12 @@ "TARGET_Z10 && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]), INTVAL (operands[2]))" - "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3" + { + static char buffer[256]; + sprintf (buffer, "r<noxa>sbg\t%%0,%%1,%%<bfstart>2,%%<bfend>2,%ld", + 64 - INTVAL (operands[3])); + return buffer; + } [(set_attr "op_type" "RIE")]) ; rosbg, rxsbg @@ -4309,7 +4314,12 @@ (match_operand:GPR 3 "nonimmediate_operand" "0"))) (clobber (reg:CC CC_REGNUM))] "TARGET_Z10" - "r<noxa>sbg\t%0,%1,<bitoff>,63-%2,%2" + { + static char buffer[256]; + sprintf (buffer, "r<noxa>sbg\t%%0,%%1,<bitoff>,%ld,%%2", + 63 - INTVAL (operands[2])); + return buffer; + } [(set_attr "op_type" "RIE")]) ;; unsigned {int,long} a, b @@ -4325,7 +4335,33 @@ (match_operand:GPR 3 "nonimmediate_operand" "0"))) (clobber (reg:CC CC_REGNUM))] "TARGET_Z10" - "r<noxa>sbg\t%0,%1,<bitoff_plus>%2,63,64-%2" + { + static char buffer[256]; + sprintf (buffer, "r<noxa>sbg\t%%0,%%1,%ld,63,%ld", + <bitoff_plus> INTVAL (operands[2]), 64 - INTVAL (operands[2])); + return buffer; + } + [(set_attr "op_type" "RIE")]) + +; rosbg, rxsbg +(define_insn "*r<noxa>sbg_sidi_srl" + [(set (match_operand:SI 0 "nonimmediate_operand" "=d") + (IXOR:SI + (subreg:SI + (zero_extract:DI + (match_operand:DI 1 "nonimmediate_operand" "d") + (const_int 32) + (match_operand:DI 2 "immediate_operand" "")) + 4) + (match_operand:SI 3 "nonimmediate_operand" "0"))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_Z10" + { + static char buffer[256]; + sprintf (buffer, "r<noxa>sbg\t%%0,%%1,%ld,63,%ld", + 64 - INTVAL (operands[2]), 32 + INTVAL (operands[2])); + return buffer; + } [(set_attr "op_type" "RIE")]) ;; These two are generated by combine for s.bf &= val. diff --git a/gcc/testsuite/gcc.target/s390/md/rXsbg_mode_sXl.c b/gcc/testsuite/gcc.target/s390/md/rXsbg_mode_sXl.c index 824ce39dfd9..600914280e5 100644 --- a/gcc/testsuite/gcc.target/s390/md/rXsbg_mode_sXl.c +++ b/gcc/testsuite/gcc.target/s390/md/rXsbg_mode_sXl.c @@ -39,28 +39,28 @@ rosbg_si_sll (unsigned int a, unsigned int b) { return a | (b << 1); } -/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,32,63-1,1" 1 } } */ +/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,32,62,1" 1 } } */ __attribute__ ((noinline)) unsigned int rosbg_si_srl (unsigned int a, unsigned int b) { return a | (b >> 2); } -/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,32\\+2,63,64-2" 1 } } */ +/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,34,63,62" 1 } } */ __attribute__ ((noinline)) unsigned int rxsbg_si_sll (unsigned int a, unsigned int b) { return a ^ (b << 1); } -/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,32,63-1,1" 1 } } */ +/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,32,62,1" 1 } } */ __attribute__ ((noinline)) unsigned int rxsbg_si_srl (unsigned int a, unsigned int b) { return a ^ (b >> 2); } -/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,32\\+2,63,64-2" 1 } } */ +/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,34,63,62" 1 } } */ __attribute__ ((noinline)) unsigned long long di_sll (unsigned long long x) @@ -79,28 +79,28 @@ rosbg_di_sll (unsigned long long a, unsigned long long b) { return a | (b << 1); } -/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,0,63-1,1" 1 } } */ +/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,0,62,1" 1 } } */ __attribute__ ((noinline)) unsigned long long rosbg_di_srl (unsigned long long a, unsigned long long b) { return a | (b >> 2); } -/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,2,63,64-2" 1 } } */ +/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,2,63,62" 1 } } */ __attribute__ ((noinline)) unsigned long long rxsbg_di_sll (unsigned long long a, unsigned long long b) { return a ^ (b << 1); } -/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,0,63-1,1" 1 } } */ +/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,0,62,1" 1 } } */ __attribute__ ((noinline)) unsigned long long rxsbg_di_srl (unsigned long long a, unsigned long long b) { return a ^ (b >> 2); } -/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,2,63,64-2" 1 } } */ +/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,2,63,62" 1 } } */ int main (void) diff --git a/gcc/testsuite/gcc.target/s390/risbg-ll-2.c b/gcc/testsuite/gcc.target/s390/risbg-ll-2.c index 6588dc7ae96..754c17311dd 100644 --- a/gcc/testsuite/gcc.target/s390/risbg-ll-2.c +++ b/gcc/testsuite/gcc.target/s390/risbg-ll-2.c @@ -114,7 +114,7 @@ i32 f9 (i64 v_x, i32 v_y) i32 f10 (i64 v_x, i32 v_y) { /* { dg-final { scan-assembler "f10:\n\tsrlg\t%r2,%r2,48\n\trosbg\t%r2,%r3,32,39,0" { target { lp64 } } } } */ - /* { dg-final { scan-assembler "f10:\n\tnilf\t%r4,4278190080\n\trosbg\t%r4,%r2,32\\\+16,63,64-16" { target { ! lp64 } } } } */ + /* { dg-final { scan-assembler "f10:\n\tnilf\t%r4,4278190080\n\trosbg\t%r4,%r2,48,63,48" { target { ! lp64 } } } } */ i64 v_shr6 = ((ui64)v_x) >> 48; i32 v_conv = (ui32)v_shr6; i32 v_and1 = v_y & -16777216; -- 2.19.1