diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 566f560..1b81e40 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,16 @@
+2018-12-12  Wei Xiao  <wei3.xiao@intel.com>
+
+	* common/config/i386/i386-common.c (processor_names): Add cascadelake.
+	(processor_alias_table): Add cascadelake.
+	* config.gcc: Add -march=cascadelake.
+	* config/i386/i386-c.c (ix86_target_macros_internal): Handle cascadelake.
+	* config/i386/i386.c (Add m_CASCADELAKE): New.
+	(processor_cost_table): Add cascadelake.
+	(get_builtin_code_for_version): Handle cascadelake.
+	* config/i386/i386.h (TARGET_CASCADELAKE, PROCESSOR_CASCADELAKE): New.
+	(PTA_CASCADELAKE): Ditto.
+	* doc/invoke.texi: Add -march=cascadelake.
+
 2018-12-11  Jakub Jelinek  <jakub@redhat.com>
 
 	PR tree-optimization/88444
@@ -3442,7 +3455,7 @@
 	* vr-values.c (vr_values::extract_range_from_comparison):
 	Clear equiv for constant singleton ranges.
 
-2018-11-12 Wei Xiao <wei3.xiao@intel.com>
+2018-11-12  Wei Xiao  <wei3.xiao@intel.com>
 
 	* config/i386/sse.md: Combine VFIXUPIMM* patterns
 	(<avx512>_fixupimm<mode>_maskz<round_saeonly_expand_name>): Update.
@@ -4693,7 +4706,7 @@
 	(pass_inc_dec::execute): Allocate and release
 	reg_next_debug_use.
 
-2018-11-06 Wei Xiao <wei3.xiao@intel.com>
+2018-11-06  Wei Xiao  <wei3.xiao@intel.com>
 
 	* config/i386/avx512fintrin.h: Update VFIXUPIMM* intrinsics.
 	(_mm512_fixupimm_round_pd): Update parameters and builtin.
diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c
index 4238b43..f7a1fea 100644
--- a/gcc/common/config/i386/i386-common.c
+++ b/gcc/common/config/i386/i386-common.c
@@ -1504,6 +1504,7 @@ const char *const processor_names[] =
   "cannonlake",
   "icelake-client",
   "icelake-server",
+  "cascadelake",
   "intel",
   "geode",
   "k6",
@@ -1584,6 +1585,8 @@ const pta processor_alias_table[] =
     PTA_ICELAKE_CLIENT},
   {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
     PTA_ICELAKE_SERVER},
+  {"cascadelake", PROCESSOR_CASCADELAKE, CPU_HASWELL,
+    PTA_CASCADELAKE},
   {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
   {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
   {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 47b2917..3122a0c 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -662,7 +662,7 @@ bdver3 bdver4 znver1 znver2 btver1 btver2 k8 k8-sse3 opteron \
 opteron-sse3 nocona core2 corei7 corei7-avx core-avx-i core-avx2 atom \
 slm nehalem westmere sandybridge ivybridge haswell broadwell bonnell \
 silvermont knl knm skylake-avx512 cannonlake icelake-client icelake-server \
-skylake goldmont goldmont-plus tremont x86-64 native"
+skylake goldmont goldmont-plus tremont cascadelake x86-64 native"
 
 # Additional x86 processors supported by --with-cpu=.  Each processor
 # MUST be separated by exactly one space.
diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c
index 16c6a2d..5c327dc 100644
--- a/gcc/config/i386/i386-c.c
+++ b/gcc/config/i386/i386-c.c
@@ -218,6 +218,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
       def_or_undef (parse_in, "__icelake_server");
       def_or_undef (parse_in, "__icelake_server__");
       break;
+    case PROCESSOR_CASCADELAKE:
+      def_or_undef (parse_in, "__cascadelake");
+      def_or_undef (parse_in, "__cascadelake__");
+      break;
     /* use PROCESSOR_max to not set/unset the arch macro.  */
     case PROCESSOR_max:
       break;
@@ -363,6 +367,9 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
     case PROCESSOR_LAKEMONT:
       def_or_undef (parse_in, "__tune_lakemont__");
       break;
+    case PROCESSOR_CASCADELAKE:
+      def_or_undef (parse_in, "__tune_cascadelake__");
+      break;
     case PROCESSOR_INTEL:
     case PROCESSOR_GENERIC:
       break;
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index e86c39e..caa701f 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -148,8 +148,9 @@ const struct processor_costs *ix86_cost = NULL;
 #define m_CANNONLAKE (HOST_WIDE_INT_1U<<PROCESSOR_CANNONLAKE)
 #define m_ICELAKE_CLIENT (HOST_WIDE_INT_1U<<PROCESSOR_ICELAKE_CLIENT)
 #define m_ICELAKE_SERVER (HOST_WIDE_INT_1U<<PROCESSOR_ICELAKE_SERVER)
+#define m_CASCADELAKE (HOST_WIDE_INT_1U<<PROCESSOR_CASCADELAKE)
 #define m_CORE_AVX512 (m_SKYLAKE_AVX512 | m_CANNONLAKE \
-		       | m_ICELAKE_CLIENT | m_ICELAKE_SERVER)
+		       | m_ICELAKE_CLIENT | m_ICELAKE_SERVER | m_CASCADELAKE)
 #define m_CORE_AVX2 (m_HASWELL | m_SKYLAKE | m_CORE_AVX512)
 #define m_CORE_ALL (m_CORE2 | m_NEHALEM  | m_SANDYBRIDGE | m_CORE_AVX2)
 #define m_GOLDMONT (HOST_WIDE_INT_1U<<PROCESSOR_GOLDMONT)
@@ -898,6 +899,7 @@ static const struct processor_costs *processor_cost_table[] =
   &skylake_cost,
   &skylake_cost,
   &skylake_cost,
+  &skylake_cost,
   &intel_cost,
   &geode_cost,
   &k6_cost,
@@ -31644,6 +31646,10 @@ get_builtin_code_for_version (tree decl, tree *predicate_list)
 	      arg_str = "icelake-server";
 	      priority = P_PROC_AVX512F;
 	      break;
+	    case PROCESSOR_CASCADELAKE:
+	      arg_str = "cascadelake";
+	      priority = P_PROC_AVX512F;
+	      break;
 	    case PROCESSOR_BONNELL:
 	      arg_str = "bonnell";
 	      priority = P_PROC_SSSE3;
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index b9e726e..64fc5d4 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -407,6 +407,7 @@ extern const struct processor_costs ix86_size_cost;
 #define TARGET_CANNONLAKE (ix86_tune == PROCESSOR_CANNONLAKE)
 #define TARGET_ICELAKE_CLIENT (ix86_tune == PROCESSOR_ICELAKE_CLIENT)
 #define TARGET_ICELAKE_SERVER (ix86_tune == PROCESSOR_ICELAKE_SERVER)
+#define TARGET_CASCADELAKE (ix86_tune == PROCESSOR_CASCADELAKE)
 #define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL)
 #define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC)
 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
@@ -2261,6 +2262,7 @@ enum processor_type
   PROCESSOR_CANNONLAKE,
   PROCESSOR_ICELAKE_CLIENT,
   PROCESSOR_ICELAKE_SERVER,
+  PROCESSOR_CASCADELAKE,
   PROCESSOR_INTEL,
   PROCESSOR_GEODE,
   PROCESSOR_K6,
@@ -2377,6 +2379,7 @@ const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT
 const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
   | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
   | PTA_CLWB;
+const wide_int_bitmask PTA_CASCADELAKE = PTA_SKYLAKE_AVX512 | PTA_AVX512VNNI;
 const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
   | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
   | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 42d2c53..1bdeac3 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -27000,6 +27000,12 @@ AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ,
 AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES, PCONFIG and WBNOINVD instruction
 set support.
 
+@item cascadelake
+Intel Cascadelake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
+SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
+BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
+AVX512VL, AVX512BW, AVX512DQ, AVX512CD and AVX512VNNI instruction set support.
+
 @item k6
 AMD K6 CPU with MMX instruction set support.
 
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index bfe527a..ba7bf80 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2018-12-12  Wei Xiao  <wei3.xiao@intel.com>
+
+	* gcc.target/i386/funcspec-56.inc: Handle new march.
+
 2018-12-11  Steven G. Kargl  <kargl@gcc.gnu.org>
 
 	PR fortran/88155
@@ -2548,7 +2552,7 @@
 	* gcc.target/i386/pr18041-1.c: New testcase.
 	* gcc.target/i386/pr18041-2.c: Likewise.
 
-2018-11-06 Wei Xiao <wei3.xiao@intel.com>
+2018-11-06  Wei Xiao  <wei3.xiao@intel.com>
 
 	* gcc.target/i386/avx-1.c: Update tests for VFIXUPIMM* intrinsics.
 	* gcc.target/i386/avx512f-vfixupimmpd-1.c: Ditto.
diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
index 437b12f..0eb83a7 100644
--- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
+++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
@@ -150,6 +150,7 @@ extern void test_arch_skylake_avx512 (void)	__attribute__((__target__("arch=skyl
 extern void test_arch_cannonlake (void)		__attribute__((__target__("arch=cannonlake")));
 extern void test_arch_icelake_client (void)	__attribute__((__target__("arch=icelake-client")));
 extern void test_arch_icelake_server (void)	__attribute__((__target__("arch=icelake-server")));
+extern void test_arch_cascadelake (void)	__attribute__((__target__("arch=cascadelake")));
 extern void test_arch_k8 (void)			__attribute__((__target__("arch=k8")));
 extern void test_arch_k8_sse3 (void)		__attribute__((__target__("arch=k8-sse3")));
 extern void test_arch_opteron (void)		__attribute__((__target__("arch=opteron")));