On 2/10/19, H.J. Lu <hjl.to...@gmail.com> wrote:
> Emulate MMX ssse3_pmulhrswv4hi3 with SSE. Only SSE register source
> operand is allowed.
>
> PR target/89021
> * config/i386/sse.md (*ssse3_pmulhrswv4hi3): Add SSE emulation.
OK.
Uros.
> ---
> gcc/config/i386/sse.md | 20 +++++++++++++-------
> 1 file changed, 13 insertions(+), 7 deletions(-)
>
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index 8b13a76da72..0d0f84705d1 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -15774,25 +15774,31 @@
> (set_attr "mode" "<sseinsnmode>")])
>
> (define_insn "*ssse3_pmulhrswv4hi3"
> - [(set (match_operand:V4HI 0 "register_operand" "=y")
> + [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv")
> (truncate:V4HI
> (lshiftrt:V4SI
> (plus:V4SI
> (lshiftrt:V4SI
> (mult:V4SI
> (sign_extend:V4SI
> - (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
> + (match_operand:V4HI 1 "nonimmediate_operand" "%0,0,Yv"))
> (sign_extend:V4SI
> - (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
> + (match_operand:V4HI 2 "nonimmediate_operand" "ym,x,Yv")))
> (const_int 14))
> (match_operand:V4HI 3 "const1_operand"))
> (const_int 1))))]
> - "TARGET_SSSE3 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> - "pmulhrsw\t{%2, %0|%0, %2}"
> - [(set_attr "type" "sseimul")
> + "(TARGET_MMX || TARGET_MMX_WITH_SSE)
> + && TARGET_SSSE3
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> + "@
> + pmulhrsw\t{%2, %0|%0, %2}
> + pmulhrsw\t{%2, %0|%0, %2}
> + vpmulhrsw\t{%2, %1, %0|%0, %1, %2}"
> + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
> + (set_attr "type" "sseimul")
> (set_attr "prefix_extra" "1")
> (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p
> (insn)"))
> - (set_attr "mode" "DI")])
> + (set_attr "mode" "DI,TI,TI")])
>
> (define_insn "<ssse3_avx2>_pshufb<mode>3<mask_name>"
> [(set (match_operand:VI1_AVX512 0 "register_operand" "=x,x,v")
> --
> 2.20.1
>
>
