On Mon, Feb 11, 2019 at 11:55 PM H.J. Lu <hjl.to...@gmail.com> wrote:
>
> Emulate MMX mmx_pmovmskb with SSE by zero-extending result of SSE pmovmskb
> from QImode to SImode. Only SSE register source operand is allowed.
>
> PR target/89021
> * config/i386/mmx.md (mmx_pmovmskb): Changed to
> define_insn_and_split to support SSE emulation.
> ---
> gcc/config/i386/mmx.md | 30 +++++++++++++++++++++++-------
> 1 file changed, 23 insertions(+), 7 deletions(-)
>
> diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
> index 4cf008e99c7..d9ff70884bd 100644
> --- a/gcc/config/i386/mmx.md
> +++ b/gcc/config/i386/mmx.md
> @@ -1799,14 +1799,30 @@
> [(set_attr "type" "mmxshft")
> (set_attr "mode" "DI")])
>
> -(define_insn "mmx_pmovmskb"
> - [(set (match_operand:SI 0 "register_operand" "=r")
> - (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")]
> +(define_insn_and_split "mmx_pmovmskb"
> + [(set (match_operand:SI 0 "register_operand" "=r,r")
> + (unspec:SI [(match_operand:V8QI 1 "register_operand" "y,x")]
> UNSPEC_MOVMSK))]
> - "TARGET_SSE || TARGET_3DNOW_A"
> - "pmovmskb\t{%1, %0|%0, %1}"
> - [(set_attr "type" "mmxcvt")
> - (set_attr "mode" "DI")])
> + "(TARGET_MMX || TARGET_MMX_WITH_SSE)
> + && (TARGET_SSE || TARGET_3DNOW_A)"
> + "@
> + pmovmskb\t{%1, %0|%0, %1}
> + #"
> + "TARGET_MMX_WITH_SSE && reload_completed"
> + [(set (match_dup 0)
> + (zero_extend:SI (match_dup 1)))]
> +{
> + /* Generate SSE pmovmskb and zero-extend from QImode to SImode. */
> + rtx op1 = lowpart_subreg (V16QImode, operands[1],
> + GET_MODE (operands[1]));
> + rtx insn = gen_sse2_pmovmskb (operands[0], op1);
> + emit_insn (insn);
This should be emitted explicitly from the splitter.
Uros.
> + operands[1] = lowpart_subreg (QImode, operands[0],
> + GET_MODE (operands[0]));
> +}
> + [(set_attr "mmx_isa" "native,x64")
> + (set_attr "type" "mmxcvt,ssemov")
> + (set_attr "mode" "DI,TI")])
>
> (define_expand "mmx_maskmovq"
> [(set (match_operand:V8QI 0 "memory_operand")
> --
> 2.20.1
>
