Hi,
A number of AArch64 define_expand patterns have specified constraints
for their operands. But the constraint strings are ignored at expand
time and are therefore redundant/useless. We now avoid specifying
constraints in new define_expands, but we should clean up the existing
define_expand definitions.
For example, the constraint "=w" is removed in the following case:
(define_expand "sqrt<mode>2"
[(set (match_operand:GPF_F16 0 "register_operand" "=w")
The "" marks with an empty constraint in define_expand are removed as well.
The patch is tested with the build configuration of
--target=aarch64-none-linux-gnu, and it passes gcc/testsuite.
Thanks
Dennis
gcc/ChangeLog:
2019-06-21 Dennis Zhang <dennis.zh...@arm.com>
* config/aarch64/aarch64-simd.md: Remove redundant constraints
from define_expand.
* config/aarch64/aarch64-sve.md: Likewise.
* config/aarch64/aarch64.md: Likewise.
* config/aarch64/atomics.md: Likewise.
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index df8bf1d9778..837242c7e56 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -19,8 +19,8 @@
;; <http://www.gnu.org/licenses/>.
(define_expand "mov<mode>"
- [(set (match_operand:VALL_F16 0 "nonimmediate_operand" "")
- (match_operand:VALL_F16 1 "general_operand" ""))]
+ [(set (match_operand:VALL_F16 0 "nonimmediate_operand")
+ (match_operand:VALL_F16 1 "general_operand"))]
"TARGET_SIMD"
"
/* Force the operand into a register if it is not an
@@ -39,8 +39,8 @@
)
(define_expand "movmisalign<mode>"
- [(set (match_operand:VALL 0 "nonimmediate_operand" "")
- (match_operand:VALL 1 "general_operand" ""))]
+ [(set (match_operand:VALL 0 "nonimmediate_operand")
+ (match_operand:VALL 1 "general_operand"))]
"TARGET_SIMD"
{
/* This pattern is not permitted to fail during expansion: if both arguments
@@ -652,8 +652,8 @@
[(set_attr "type" "neon_fp_rsqrts_<stype><q>")])
(define_expand "rsqrt<mode>2"
- [(set (match_operand:VALLF 0 "register_operand" "=w")
- (unspec:VALLF [(match_operand:VALLF 1 "register_operand" "w")]
+ [(set (match_operand:VALLF 0 "register_operand")
+ (unspec:VALLF [(match_operand:VALLF 1 "register_operand")]
UNSPEC_RSQRT))]
"TARGET_SIMD"
{
@@ -1025,9 +1025,9 @@
)
(define_expand "ashl<mode>3"
- [(match_operand:VDQ_I 0 "register_operand" "")
- (match_operand:VDQ_I 1 "register_operand" "")
- (match_operand:SI 2 "general_operand" "")]
+ [(match_operand:VDQ_I 0 "register_operand")
+ (match_operand:VDQ_I 1 "register_operand")
+ (match_operand:SI 2 "general_operand")]
"TARGET_SIMD"
{
int bit_width = GET_MODE_UNIT_SIZE (<MODE>mode) * BITS_PER_UNIT;
@@ -1072,9 +1072,9 @@
)
(define_expand "lshr<mode>3"
- [(match_operand:VDQ_I 0 "register_operand" "")
- (match_operand:VDQ_I 1 "register_operand" "")
- (match_operand:SI 2 "general_operand" "")]
+ [(match_operand:VDQ_I 0 "register_operand")
+ (match_operand:VDQ_I 1 "register_operand")
+ (match_operand:SI 2 "general_operand")]
"TARGET_SIMD"
{
int bit_width = GET_MODE_UNIT_SIZE (<MODE>mode) * BITS_PER_UNIT;
@@ -1119,9 +1119,9 @@
)
(define_expand "ashr<mode>3"
- [(match_operand:VDQ_I 0 "register_operand" "")
- (match_operand:VDQ_I 1 "register_operand" "")
- (match_operand:SI 2 "general_operand" "")]
+ [(match_operand:VDQ_I 0 "register_operand")
+ (match_operand:VDQ_I 1 "register_operand")
+ (match_operand:SI 2 "general_operand")]
"TARGET_SIMD"
{
int bit_width = GET_MODE_UNIT_SIZE (<MODE>mode) * BITS_PER_UNIT;
@@ -1166,9 +1166,9 @@
)
(define_expand "vashl<mode>3"
- [(match_operand:VDQ_I 0 "register_operand" "")
- (match_operand:VDQ_I 1 "register_operand" "")
- (match_operand:VDQ_I 2 "register_operand" "")]
+ [(match_operand:VDQ_I 0 "register_operand")
+ (match_operand:VDQ_I 1 "register_operand")
+ (match_operand:VDQ_I 2 "register_operand")]
"TARGET_SIMD"
{
emit_insn (gen_aarch64_simd_reg_sshl<mode> (operands[0], operands[1],
@@ -1180,9 +1180,9 @@
;; Negating individual lanes most certainly offsets the
;; gain from vectorization.
(define_expand "vashr<mode>3"
- [(match_operand:VDQ_BHSI 0 "register_operand" "")
- (match_operand:VDQ_BHSI 1 "register_operand" "")
- (match_operand:VDQ_BHSI 2 "register_operand" "")]
+ [(match_operand:VDQ_BHSI 0 "register_operand")
+ (match_operand:VDQ_BHSI 1 "register_operand")
+ (match_operand:VDQ_BHSI 2 "register_operand")]
"TARGET_SIMD"
{
rtx neg = gen_reg_rtx (<MODE>mode);
@@ -1194,9 +1194,9 @@
;; DI vector shift
(define_expand "aarch64_ashr_simddi"
- [(match_operand:DI 0 "register_operand" "=w")
- (match_operand:DI 1 "register_operand" "w")
- (match_operand:SI 2 "aarch64_shift_imm64_di" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "register_operand")
+ (match_operand:SI 2 "aarch64_shift_imm64_di")]
"TARGET_SIMD"
{
/* An arithmetic shift right by 64 fills the result with copies of the sign
@@ -1210,9 +1210,9 @@
)
(define_expand "vlshr<mode>3"
- [(match_operand:VDQ_BHSI 0 "register_operand" "")
- (match_operand:VDQ_BHSI 1 "register_operand" "")
- (match_operand:VDQ_BHSI 2 "register_operand" "")]
+ [(match_operand:VDQ_BHSI 0 "register_operand")
+ (match_operand:VDQ_BHSI 1 "register_operand")
+ (match_operand:VDQ_BHSI 2 "register_operand")]
"TARGET_SIMD"
{
rtx neg = gen_reg_rtx (<MODE>mode);
@@ -1223,9 +1223,9 @@
})
(define_expand "aarch64_lshr_simddi"
- [(match_operand:DI 0 "register_operand" "=w")
- (match_operand:DI 1 "register_operand" "w")
- (match_operand:SI 2 "aarch64_shift_imm64_di" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "register_operand")
+ (match_operand:SI 2 "aarch64_shift_imm64_di")]
"TARGET_SIMD"
{
if (INTVAL (operands[2]) == 64)
@@ -1253,9 +1253,9 @@
)
(define_expand "vec_set<mode>"
- [(match_operand:VALL_F16 0 "register_operand" "+w")
- (match_operand:<VEL> 1 "register_operand" "w")
- (match_operand:SI 2 "immediate_operand" "")]
+ [(match_operand:VALL_F16 0 "register_operand")
+ (match_operand:<VEL> 1 "register_operand")
+ (match_operand:SI 2 "immediate_operand")]
"TARGET_SIMD"
{
HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]);
@@ -1394,9 +1394,9 @@
)
(define_expand "<su><maxmin>v2di3"
- [(set (match_operand:V2DI 0 "register_operand" "")
- (MAXMIN:V2DI (match_operand:V2DI 1 "register_operand" "")
- (match_operand:V2DI 2 "register_operand" "")))]
+ [(set (match_operand:V2DI 0 "register_operand")
+ (MAXMIN:V2DI (match_operand:V2DI 1 "register_operand")
+ (match_operand:V2DI 2 "register_operand")))]
"TARGET_SIMD"
{
enum rtx_code cmp_operator;
@@ -1565,8 +1565,8 @@
)
(define_expand "move_hi_quad_<mode>"
- [(match_operand:VQ 0 "register_operand" "")
- (match_operand:<VHALF> 1 "register_operand" "")]
+ [(match_operand:VQ 0 "register_operand")
+ (match_operand:<VHALF> 1 "register_operand")]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false);
@@ -1591,9 +1591,9 @@
)
(define_expand "vec_pack_trunc_<mode>"
- [(match_operand:<VNARROWD> 0 "register_operand" "")
- (match_operand:VDN 1 "register_operand" "")
- (match_operand:VDN 2 "register_operand" "")]
+ [(match_operand:<VNARROWD> 0 "register_operand")
+ (match_operand:VDN 1 "register_operand")
+ (match_operand:VDN 2 "register_operand")]
"TARGET_SIMD"
{
rtx tempreg = gen_reg_rtx (<VDBL>mode);
@@ -1649,7 +1649,7 @@
)
(define_expand "vec_unpack<su>_hi_<mode>"
- [(match_operand:<VWIDE> 0 "register_operand" "")
+ [(match_operand:<VWIDE> 0 "register_operand")
(ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand"))]
"TARGET_SIMD"
{
@@ -1661,8 +1661,8 @@
)
(define_expand "vec_unpack<su>_lo_<mode>"
- [(match_operand:<VWIDE> 0 "register_operand" "")
- (ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand" ""))]
+ [(match_operand:<VWIDE> 0 "register_operand")
+ (ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand"))]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false);
@@ -1780,9 +1780,9 @@
)
(define_expand "vec_widen_<su>mult_lo_<mode>"
- [(match_operand:<VWIDE> 0 "register_operand" "")
- (ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand" ""))
- (ANY_EXTEND:<VWIDE> (match_operand:VQW 2 "register_operand" ""))]
+ [(match_operand:<VWIDE> 0 "register_operand")
+ (ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand"))
+ (ANY_EXTEND:<VWIDE> (match_operand:VQW 2 "register_operand"))]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false);
@@ -1807,9 +1807,9 @@
)
(define_expand "vec_widen_<su>mult_hi_<mode>"
- [(match_operand:<VWIDE> 0 "register_operand" "")
- (ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand" ""))
- (ANY_EXTEND:<VWIDE> (match_operand:VQW 2 "register_operand" ""))]
+ [(match_operand:<VWIDE> 0 "register_operand")
+ (ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand"))
+ (ANY_EXTEND:<VWIDE> (match_operand:VQW 2 "register_operand"))]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
@@ -1874,9 +1874,9 @@
)
(define_expand "div<mode>3"
- [(set (match_operand:VHSDF 0 "register_operand" "=w")
- (div:VHSDF (match_operand:VHSDF 1 "register_operand" "w")
- (match_operand:VHSDF 2 "register_operand" "w")))]
+ [(set (match_operand:VHSDF 0 "register_operand")
+ (div:VHSDF (match_operand:VHSDF 1 "register_operand")
+ (match_operand:VHSDF 2 "register_operand")))]
"TARGET_SIMD"
{
if (aarch64_emit_approx_div (operands[0], operands[1], operands[2]))
@@ -2211,8 +2211,8 @@
;; other big-endian patterns their behavior is as required.
(define_expand "vec_unpacks_lo_<mode>"
- [(match_operand:<VWIDE> 0 "register_operand" "")
- (match_operand:VQ_HSF 1 "register_operand" "")]
+ [(match_operand:<VWIDE> 0 "register_operand")
+ (match_operand:VQ_HSF 1 "register_operand")]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false);
@@ -2234,8 +2234,8 @@
)
(define_expand "vec_unpacks_hi_<mode>"
- [(match_operand:<VWIDE> 0 "register_operand" "")
- (match_operand:VQ_HSF 1 "register_operand" "")]
+ [(match_operand:<VWIDE> 0 "register_operand")
+ (match_operand:VQ_HSF 1 "register_operand")]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
@@ -2287,9 +2287,9 @@
)
(define_expand "aarch64_float_truncate_hi_<Vdbl>"
- [(match_operand:<VDBL> 0 "register_operand" "=w")
- (match_operand:VDF 1 "register_operand" "0")
- (match_operand:<VWIDE> 2 "register_operand" "w")]
+ [(match_operand:<VDBL> 0 "register_operand")
+ (match_operand:VDF 1 "register_operand")
+ (match_operand:<VWIDE> 2 "register_operand")]
"TARGET_SIMD"
{
rtx (*gen) (rtx, rtx, rtx) = BYTES_BIG_ENDIAN
@@ -2382,8 +2382,8 @@
;; 'across lanes' add.
(define_expand "reduc_plus_scal_<mode>"
- [(match_operand:<VEL> 0 "register_operand" "=w")
- (unspec:VDQ_I [(match_operand:VDQ_I 1 "register_operand" "w")]
+ [(match_operand:<VEL> 0 "register_operand")
+ (unspec:VDQ_I [(match_operand:VDQ_I 1 "register_operand")]
UNSPEC_ADDV)]
"TARGET_SIMD"
{
@@ -3299,9 +3299,9 @@
(define_expand "aarch64_saddl2<mode>"
- [(match_operand:<VWIDE> 0 "register_operand" "=w")
- (match_operand:VQW 1 "register_operand" "w")
- (match_operand:VQW 2 "register_operand" "w")]
+ [(match_operand:<VWIDE> 0 "register_operand")
+ (match_operand:VQW 1 "register_operand")
+ (match_operand:VQW 2 "register_operand")]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
@@ -3311,9 +3311,9 @@
})
(define_expand "aarch64_uaddl2<mode>"
- [(match_operand:<VWIDE> 0 "register_operand" "=w")
- (match_operand:VQW 1 "register_operand" "w")
- (match_operand:VQW 2 "register_operand" "w")]
+ [(match_operand:<VWIDE> 0 "register_operand")
+ (match_operand:VQW 1 "register_operand")
+ (match_operand:VQW 2 "register_operand")]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
@@ -3323,9 +3323,9 @@
})
(define_expand "aarch64_ssubl2<mode>"
- [(match_operand:<VWIDE> 0 "register_operand" "=w")
- (match_operand:VQW 1 "register_operand" "w")
- (match_operand:VQW 2 "register_operand" "w")]
+ [(match_operand:<VWIDE> 0 "register_operand")
+ (match_operand:VQW 1 "register_operand")
+ (match_operand:VQW 2 "register_operand")]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
@@ -3335,9 +3335,9 @@
})
(define_expand "aarch64_usubl2<mode>"
- [(match_operand:<VWIDE> 0 "register_operand" "=w")
- (match_operand:VQW 1 "register_operand" "w")
- (match_operand:VQW 2 "register_operand" "w")]
+ [(match_operand:<VWIDE> 0 "register_operand")
+ (match_operand:VQW 1 "register_operand")
+ (match_operand:VQW 2 "register_operand")]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
@@ -3360,10 +3360,10 @@
;; <su><addsub>w<q>.
(define_expand "widen_ssum<mode>3"
- [(set (match_operand:<VDBLW> 0 "register_operand" "")
+ [(set (match_operand:<VDBLW> 0 "register_operand")
(plus:<VDBLW> (sign_extend:<VDBLW>
- (match_operand:VQW 1 "register_operand" ""))
- (match_operand:<VDBLW> 2 "register_operand" "")))]
+ (match_operand:VQW 1 "register_operand"))
+ (match_operand:<VDBLW> 2 "register_operand")))]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false);
@@ -3377,10 +3377,10 @@
)
(define_expand "widen_ssum<mode>3"
- [(set (match_operand:<VWIDE> 0 "register_operand" "")
+ [(set (match_operand:<VWIDE> 0 "register_operand")
(plus:<VWIDE> (sign_extend:<VWIDE>
- (match_operand:VD_BHSI 1 "register_operand" ""))
- (match_operand:<VWIDE> 2 "register_operand" "")))]
+ (match_operand:VD_BHSI 1 "register_operand"))
+ (match_operand:<VWIDE> 2 "register_operand")))]
"TARGET_SIMD"
{
emit_insn (gen_aarch64_saddw<mode> (operands[0], operands[2], operands[1]));
@@ -3388,10 +3388,10 @@
})
(define_expand "widen_usum<mode>3"
- [(set (match_operand:<VDBLW> 0 "register_operand" "")
+ [(set (match_operand:<VDBLW> 0 "register_operand")
(plus:<VDBLW> (zero_extend:<VDBLW>
- (match_operand:VQW 1 "register_operand" ""))
- (match_operand:<VDBLW> 2 "register_operand" "")))]
+ (match_operand:VQW 1 "register_operand"))
+ (match_operand:<VDBLW> 2 "register_operand")))]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false);
@@ -3405,10 +3405,10 @@
)
(define_expand "widen_usum<mode>3"
- [(set (match_operand:<VWIDE> 0 "register_operand" "")
+ [(set (match_operand:<VWIDE> 0 "register_operand")
(plus:<VWIDE> (zero_extend:<VWIDE>
- (match_operand:VD_BHSI 1 "register_operand" ""))
- (match_operand:<VWIDE> 2 "register_operand" "")))]
+ (match_operand:VD_BHSI 1 "register_operand"))
+ (match_operand:<VWIDE> 2 "register_operand")))]
"TARGET_SIMD"
{
emit_insn (gen_aarch64_uaddw<mode> (operands[0], operands[2], operands[1]));
@@ -3486,9 +3486,9 @@
)
(define_expand "aarch64_saddw2<mode>"
- [(match_operand:<VWIDE> 0 "register_operand" "=w")
- (match_operand:<VWIDE> 1 "register_operand" "w")
- (match_operand:VQW 2 "register_operand" "w")]
+ [(match_operand:<VWIDE> 0 "register_operand")
+ (match_operand:<VWIDE> 1 "register_operand")
+ (match_operand:VQW 2 "register_operand")]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
@@ -3498,9 +3498,9 @@
})
(define_expand "aarch64_uaddw2<mode>"
- [(match_operand:<VWIDE> 0 "register_operand" "=w")
- (match_operand:<VWIDE> 1 "register_operand" "w")
- (match_operand:VQW 2 "register_operand" "w")]
+ [(match_operand:<VWIDE> 0 "register_operand")
+ (match_operand:<VWIDE> 1 "register_operand")
+ (match_operand:VQW 2 "register_operand")]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
@@ -3511,9 +3511,9 @@
(define_expand "aarch64_ssubw2<mode>"
- [(match_operand:<VWIDE> 0 "register_operand" "=w")
- (match_operand:<VWIDE> 1 "register_operand" "w")
- (match_operand:VQW 2 "register_operand" "w")]
+ [(match_operand:<VWIDE> 0 "register_operand")
+ (match_operand:<VWIDE> 1 "register_operand")
+ (match_operand:VQW 2 "register_operand")]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
@@ -3523,9 +3523,9 @@
})
(define_expand "aarch64_usubw2<mode>"
- [(match_operand:<VWIDE> 0 "register_operand" "=w")
- (match_operand:<VWIDE> 1 "register_operand" "w")
- (match_operand:VQW 2 "register_operand" "w")]
+ [(match_operand:<VWIDE> 0 "register_operand")
+ (match_operand:<VWIDE> 1 "register_operand")
+ (match_operand:VQW 2 "register_operand")]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
@@ -4058,10 +4058,10 @@
)
(define_expand "aarch64_sqdmlal2<mode>"
- [(match_operand:<VWIDE> 0 "register_operand" "=w")
- (match_operand:<VWIDE> 1 "register_operand" "w")
- (match_operand:VQ_HSI 2 "register_operand" "w")
- (match_operand:VQ_HSI 3 "register_operand" "w")]
+ [(match_operand:<VWIDE> 0 "register_operand")
+ (match_operand:<VWIDE> 1 "register_operand")
+ (match_operand:VQ_HSI 2 "register_operand")
+ (match_operand:VQ_HSI 3 "register_operand")]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
@@ -4071,10 +4071,10 @@
})
(define_expand "aarch64_sqdmlsl2<mode>"
- [(match_operand:<VWIDE> 0 "register_operand" "=w")
- (match_operand:<VWIDE> 1 "register_operand" "w")
- (match_operand:VQ_HSI 2 "register_operand" "w")
- (match_operand:VQ_HSI 3 "register_operand" "w")]
+ [(match_operand:<VWIDE> 0 "register_operand")
+ (match_operand:<VWIDE> 1 "register_operand")
+ (match_operand:VQ_HSI 2 "register_operand")
+ (match_operand:VQ_HSI 3 "register_operand")]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
@@ -4138,11 +4138,11 @@
)
(define_expand "aarch64_sqdmlal2_lane<mode>"
- [(match_operand:<VWIDE> 0 "register_operand" "=w")
- (match_operand:<VWIDE> 1 "register_operand" "w")
- (match_operand:VQ_HSI 2 "register_operand" "w")
- (match_operand:<VCOND> 3 "register_operand" "<vwx>")
- (match_operand:SI 4 "immediate_operand" "i")]
+ [(match_operand:<VWIDE> 0 "register_operand")
+ (match_operand:<VWIDE> 1 "register_operand")
+ (match_operand:VQ_HSI 2 "register_operand")
+ (match_operand:<VCOND> 3 "register_operand")
+ (match_operand:SI 4 "immediate_operand")]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
@@ -4153,11 +4153,11 @@
})
(define_expand "aarch64_sqdmlal2_laneq<mode>"
- [(match_operand:<VWIDE> 0 "register_operand" "=w")
- (match_operand:<VWIDE> 1 "register_operand" "w")
- (match_operand:VQ_HSI 2 "register_operand" "w")
- (match_operand:<VCONQ> 3 "register_operand" "<vwx>")
- (match_operand:SI 4 "immediate_operand" "i")]
+ [(match_operand:<VWIDE> 0 "register_operand")
+ (match_operand:<VWIDE> 1 "register_operand")
+ (match_operand:VQ_HSI 2 "register_operand")
+ (match_operand:<VCONQ> 3 "register_operand")
+ (match_operand:SI 4 "immediate_operand")]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
@@ -4168,11 +4168,11 @@
})
(define_expand "aarch64_sqdmlsl2_lane<mode>"
- [(match_operand:<VWIDE> 0 "register_operand" "=w")
- (match_operand:<VWIDE> 1 "register_operand" "w")
- (match_operand:VQ_HSI 2 "register_operand" "w")
- (match_operand:<VCOND> 3 "register_operand" "<vwx>")
- (match_operand:SI 4 "immediate_operand" "i")]
+ [(match_operand:<VWIDE> 0 "register_operand")
+ (match_operand:<VWIDE> 1 "register_operand")
+ (match_operand:VQ_HSI 2 "register_operand")
+ (match_operand:<VCOND> 3 "register_operand")
+ (match_operand:SI 4 "immediate_operand")]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
@@ -4183,11 +4183,11 @@
})
(define_expand "aarch64_sqdmlsl2_laneq<mode>"
- [(match_operand:<VWIDE> 0 "register_operand" "=w")
- (match_operand:<VWIDE> 1 "register_operand" "w")
- (match_operand:VQ_HSI 2 "register_operand" "w")
- (match_operand:<VCONQ> 3 "register_operand" "<vwx>")
- (match_operand:SI 4 "immediate_operand" "i")]
+ [(match_operand:<VWIDE> 0 "register_operand")
+ (match_operand:<VWIDE> 1 "register_operand")
+ (match_operand:VQ_HSI 2 "register_operand")
+ (match_operand:<VCONQ> 3 "register_operand")
+ (match_operand:SI 4 "immediate_operand")]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
@@ -4217,10 +4217,10 @@
)
(define_expand "aarch64_sqdmlal2_n<mode>"
- [(match_operand:<VWIDE> 0 "register_operand" "=w")
- (match_operand:<VWIDE> 1 "register_operand" "w")
- (match_operand:VQ_HSI 2 "register_operand" "w")
- (match_operand:<VEL> 3 "register_operand" "w")]
+ [(match_operand:<VWIDE> 0 "register_operand")
+ (match_operand:<VWIDE> 1 "register_operand")
+ (match_operand:VQ_HSI 2 "register_operand")
+ (match_operand:<VEL> 3 "register_operand")]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
@@ -4231,10 +4231,10 @@
})
(define_expand "aarch64_sqdmlsl2_n<mode>"
- [(match_operand:<VWIDE> 0 "register_operand" "=w")
- (match_operand:<VWIDE> 1 "register_operand" "w")
- (match_operand:VQ_HSI 2 "register_operand" "w")
- (match_operand:<VEL> 3 "register_operand" "w")]
+ [(match_operand:<VWIDE> 0 "register_operand")
+ (match_operand:<VWIDE> 1 "register_operand")
+ (match_operand:VQ_HSI 2 "register_operand")
+ (match_operand:<VEL> 3 "register_operand")]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
@@ -4386,9 +4386,9 @@
)
(define_expand "aarch64_sqdmull2<mode>"
- [(match_operand:<VWIDE> 0 "register_operand" "=w")
- (match_operand:VQ_HSI 1 "register_operand" "w")
- (match_operand:VQ_HSI 2 "register_operand" "w")]
+ [(match_operand:<VWIDE> 0 "register_operand")
+ (match_operand:VQ_HSI 1 "register_operand")
+ (match_operand:VQ_HSI 2 "register_operand")]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
@@ -4446,10 +4446,10 @@
)
(define_expand "aarch64_sqdmull2_lane<mode>"
- [(match_operand:<VWIDE> 0 "register_operand" "=w")
- (match_operand:VQ_HSI 1 "register_operand" "w")
- (match_operand:<VCOND> 2 "register_operand" "<vwx>")
- (match_operand:SI 3 "immediate_operand" "i")]
+ [(match_operand:<VWIDE> 0 "register_operand")
+ (match_operand:VQ_HSI 1 "register_operand")
+ (match_operand:<VCOND> 2 "register_operand")
+ (match_operand:SI 3 "immediate_operand")]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
@@ -4460,10 +4460,10 @@
})
(define_expand "aarch64_sqdmull2_laneq<mode>"
- [(match_operand:<VWIDE> 0 "register_operand" "=w")
- (match_operand:VQ_HSI 1 "register_operand" "w")
- (match_operand:<VCONQ> 2 "register_operand" "<vwx>")
- (match_operand:SI 3 "immediate_operand" "i")]
+ [(match_operand:<VWIDE> 0 "register_operand")
+ (match_operand:VQ_HSI 1 "register_operand")
+ (match_operand:<VCONQ> 2 "register_operand")
+ (match_operand:SI 3 "immediate_operand")]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
@@ -4494,9 +4494,9 @@
)
(define_expand "aarch64_sqdmull2_n<mode>"
- [(match_operand:<VWIDE> 0 "register_operand" "=w")
- (match_operand:VQ_HSI 1 "register_operand" "w")
- (match_operand:<VEL> 2 "register_operand" "w")]
+ [(match_operand:<VWIDE> 0 "register_operand")
+ (match_operand:VQ_HSI 1 "register_operand")
+ (match_operand:<VEL> 2 "register_operand")]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
@@ -4898,8 +4898,8 @@
;; sqrt
(define_expand "sqrt<mode>2"
- [(set (match_operand:VHSDF 0 "register_operand" "=w")
- (sqrt:VHSDF (match_operand:VHSDF 1 "register_operand" "w")))]
+ [(set (match_operand:VHSDF 0 "register_operand")
+ (sqrt:VHSDF (match_operand:VHSDF 1 "register_operand")))]
"TARGET_SIMD"
{
if (aarch64_emit_approx_sqrt (operands[0], operands[1], false))
@@ -4952,8 +4952,8 @@
)
(define_expand "vec_load_lanesoi<mode>"
- [(set (match_operand:OI 0 "register_operand" "=w")
- (unspec:OI [(match_operand:OI 1 "aarch64_simd_struct_operand" "Utv")
+ [(set (match_operand:OI 0 "register_operand")
+ (unspec:OI [(match_operand:OI 1 "aarch64_simd_struct_operand")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_LD2))]
"TARGET_SIMD"
@@ -4996,8 +4996,8 @@
)
(define_expand "vec_store_lanesoi<mode>"
- [(set (match_operand:OI 0 "aarch64_simd_struct_operand" "=Utv")
- (unspec:OI [(match_operand:OI 1 "register_operand" "w")
+ [(set (match_operand:OI 0 "aarch64_simd_struct_operand")
+ (unspec:OI [(match_operand:OI 1 "register_operand")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_ST2))]
"TARGET_SIMD"
@@ -5050,8 +5050,8 @@
)
(define_expand "vec_load_lanesci<mode>"
- [(set (match_operand:CI 0 "register_operand" "=w")
- (unspec:CI [(match_operand:CI 1 "aarch64_simd_struct_operand" "Utv")
+ [(set (match_operand:CI 0 "register_operand")
+ (unspec:CI [(match_operand:CI 1 "aarch64_simd_struct_operand")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_LD3))]
"TARGET_SIMD"
@@ -5094,8 +5094,8 @@
)
(define_expand "vec_store_lanesci<mode>"
- [(set (match_operand:CI 0 "aarch64_simd_struct_operand" "=Utv")
- (unspec:CI [(match_operand:CI 1 "register_operand" "w")
+ [(set (match_operand:CI 0 "aarch64_simd_struct_operand")
+ (unspec:CI [(match_operand:CI 1 "register_operand")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_ST3))]
"TARGET_SIMD"
@@ -5148,8 +5148,8 @@
)
(define_expand "vec_load_lanesxi<mode>"
- [(set (match_operand:XI 0 "register_operand" "=w")
- (unspec:XI [(match_operand:XI 1 "aarch64_simd_struct_operand" "Utv")
+ [(set (match_operand:XI 0 "register_operand")
+ (unspec:XI [(match_operand:XI 1 "aarch64_simd_struct_operand")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_LD4))]
"TARGET_SIMD"
@@ -5192,8 +5192,8 @@
)
(define_expand "vec_store_lanesxi<mode>"
- [(set (match_operand:XI 0 "aarch64_simd_struct_operand" "=Utv")
- (unspec:XI [(match_operand:XI 1 "register_operand" "w")
+ [(set (match_operand:XI 0 "aarch64_simd_struct_operand")
+ (unspec:XI [(match_operand:XI 1 "register_operand")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_ST4))]
"TARGET_SIMD"
@@ -5238,8 +5238,8 @@
;; Reload patterns for AdvSIMD register list operands.
(define_expand "mov<mode>"
- [(set (match_operand:VSTRUCT 0 "nonimmediate_operand" "")
- (match_operand:VSTRUCT 1 "general_operand" ""))]
+ [(set (match_operand:VSTRUCT 0 "nonimmediate_operand")
+ (match_operand:VSTRUCT 1 "general_operand"))]
"TARGET_SIMD"
{
if (can_create_pseudo_p ())
@@ -5251,8 +5251,8 @@
(define_expand "aarch64_ld1x3<VALLDIF:mode>"
- [(match_operand:CI 0 "register_operand" "=w")
- (match_operand:DI 1 "register_operand" "r")
+ [(match_operand:CI 0 "register_operand")
+ (match_operand:DI 1 "register_operand")
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_SIMD"
{
@@ -5272,8 +5272,8 @@
)
(define_expand "aarch64_st1x2<VALLDIF:mode>"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:OI 1 "register_operand" "")
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:OI 1 "register_operand")
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_SIMD"
{
@@ -5293,8 +5293,8 @@
)
(define_expand "aarch64_st1x3<VALLDIF:mode>"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:CI 1 "register_operand" "")
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:CI 1 "register_operand")
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_SIMD"
{
@@ -5446,8 +5446,8 @@
})
(define_expand "aarch64_ld<VSTRUCT:nregs>r<VALLDIF:mode>"
- [(match_operand:VSTRUCT 0 "register_operand" "=w")
- (match_operand:DI 1 "register_operand" "w")
+ [(match_operand:VSTRUCT 0 "register_operand")
+ (match_operand:DI 1 "register_operand")
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_SIMD"
{
@@ -5521,8 +5521,8 @@
)
(define_expand "aarch64_ld<VSTRUCT:nregs><VDC:mode>"
- [(match_operand:VSTRUCT 0 "register_operand" "=w")
- (match_operand:DI 1 "register_operand" "r")
+ [(match_operand:VSTRUCT 0 "register_operand")
+ (match_operand:DI 1 "register_operand")
(unspec:VDC [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_SIMD"
{
@@ -5549,8 +5549,8 @@
})
(define_expand "aarch64_ld<VSTRUCT:nregs><VQ:mode>"
- [(match_operand:VSTRUCT 0 "register_operand" "=w")
- (match_operand:DI 1 "register_operand" "r")
+ [(match_operand:VSTRUCT 0 "register_operand")
+ (match_operand:DI 1 "register_operand")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_SIMD"
{
@@ -5562,8 +5562,8 @@
})
(define_expand "aarch64_ld1x2<VQ:mode>"
- [(match_operand:OI 0 "register_operand" "=w")
- (match_operand:DI 1 "register_operand" "r")
+ [(match_operand:OI 0 "register_operand")
+ (match_operand:DI 1 "register_operand")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_SIMD"
{
@@ -5575,8 +5575,8 @@
})
(define_expand "aarch64_ld1x2<VDC:mode>"
- [(match_operand:OI 0 "register_operand" "=w")
- (match_operand:DI 1 "register_operand" "r")
+ [(match_operand:OI 0 "register_operand")
+ (match_operand:DI 1 "register_operand")
(unspec:VDC [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_SIMD"
{
@@ -5589,10 +5589,10 @@
(define_expand "aarch64_ld<VSTRUCT:nregs>_lane<VALLDIF:mode>"
- [(match_operand:VSTRUCT 0 "register_operand" "=w")
- (match_operand:DI 1 "register_operand" "w")
- (match_operand:VSTRUCT 2 "register_operand" "0")
- (match_operand:SI 3 "immediate_operand" "i")
+ [(match_operand:VSTRUCT 0 "register_operand")
+ (match_operand:DI 1 "register_operand")
+ (match_operand:VSTRUCT 2 "register_operand")
+ (match_operand:SI 3 "immediate_operand")
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_SIMD"
{
@@ -5612,9 +5612,9 @@
;; D-register list.
(define_expand "aarch64_get_dreg<VSTRUCT:mode><VDC:mode>"
- [(match_operand:VDC 0 "register_operand" "=w")
- (match_operand:VSTRUCT 1 "register_operand" "w")
- (match_operand:SI 2 "immediate_operand" "i")]
+ [(match_operand:VDC 0 "register_operand")
+ (match_operand:VSTRUCT 1 "register_operand")
+ (match_operand:SI 2 "immediate_operand")]
"TARGET_SIMD"
{
int part = INTVAL (operands[2]);
@@ -5629,9 +5629,9 @@
;; Q-register list.
(define_expand "aarch64_get_qreg<VSTRUCT:mode><VQ:mode>"
- [(match_operand:VQ 0 "register_operand" "=w")
- (match_operand:VSTRUCT 1 "register_operand" "w")
- (match_operand:SI 2 "immediate_operand" "i")]
+ [(match_operand:VQ 0 "register_operand")
+ (match_operand:VSTRUCT 1 "register_operand")
+ (match_operand:SI 2 "immediate_operand")]
"TARGET_SIMD"
{
int part = INTVAL (operands[2]);
@@ -5870,8 +5870,8 @@
)
(define_expand "aarch64_st<VSTRUCT:nregs><VDC:mode>"
- [(match_operand:DI 0 "register_operand" "r")
- (match_operand:VSTRUCT 1 "register_operand" "w")
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:VSTRUCT 1 "register_operand")
(unspec:VDC [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_SIMD"
{
@@ -5883,8 +5883,8 @@
})
(define_expand "aarch64_st<VSTRUCT:nregs><VQ:mode>"
- [(match_operand:DI 0 "register_operand" "r")
- (match_operand:VSTRUCT 1 "register_operand" "w")
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:VSTRUCT 1 "register_operand")
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_SIMD"
{
@@ -5896,8 +5896,8 @@
})
(define_expand "aarch64_st<VSTRUCT:nregs>_lane<VALLDIF:mode>"
- [(match_operand:DI 0 "register_operand" "r")
- (match_operand:VSTRUCT 1 "register_operand" "w")
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:VSTRUCT 1 "register_operand")
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
(match_operand:SI 2 "immediate_operand")]
"TARGET_SIMD"
@@ -5933,10 +5933,10 @@
;; extend them in arm_neon.h and insert the resulting Q-regs.
(define_expand "aarch64_set_qreg<VSTRUCT:mode><VQ:mode>"
- [(match_operand:VSTRUCT 0 "register_operand" "+w")
- (match_operand:VSTRUCT 1 "register_operand" "0")
- (match_operand:VQ 2 "register_operand" "w")
- (match_operand:SI 3 "immediate_operand" "i")]
+ [(match_operand:VSTRUCT 0 "register_operand")
+ (match_operand:VSTRUCT 1 "register_operand")
+ (match_operand:VQ 2 "register_operand")
+ (match_operand:SI 3 "immediate_operand")]
"TARGET_SIMD"
{
int part = INTVAL (operands[3]);
@@ -5951,7 +5951,7 @@
;; Standard pattern name vec_init<mode><Vel>.
(define_expand "vec_init<mode><Vel>"
- [(match_operand:VALL_F16 0 "register_operand" "")
+ [(match_operand:VALL_F16 0 "register_operand")
(match_operand 1 "" "")]
"TARGET_SIMD"
{
@@ -5960,7 +5960,7 @@
})
(define_expand "vec_init<mode><Vhalf>"
- [(match_operand:VQ_NO2E 0 "register_operand" "")
+ [(match_operand:VQ_NO2E 0 "register_operand")
(match_operand 1 "" "")]
"TARGET_SIMD"
{
@@ -6039,9 +6039,9 @@
;; Standard pattern name vec_extract<mode><Vel>.
(define_expand "vec_extract<mode><Vel>"
- [(match_operand:<VEL> 0 "aarch64_simd_nonimmediate_operand" "")
- (match_operand:VALL_F16 1 "register_operand" "")
- (match_operand:SI 2 "immediate_operand" "")]
+ [(match_operand:<VEL> 0 "aarch64_simd_nonimmediate_operand")
+ (match_operand:VALL_F16 1 "register_operand")
+ (match_operand:SI 2 "immediate_operand")]
"TARGET_SIMD"
{
emit_insn
@@ -6387,11 +6387,11 @@
;; fp16fml
(define_expand "aarch64_fml<f16mac1>l<f16quad>_low<mode>"
- [(set (match_operand:VDQSF 0 "register_operand" "=w")
+ [(set (match_operand:VDQSF 0 "register_operand")
(unspec:VDQSF
- [(match_operand:VDQSF 1 "register_operand" "0")
- (match_operand:<VFMLA_W> 2 "register_operand" "w")
- (match_operand:<VFMLA_W> 3 "register_operand" "w")]
+ [(match_operand:VDQSF 1 "register_operand")
+ (match_operand:<VFMLA_W> 2 "register_operand")
+ (match_operand:<VFMLA_W> 3 "register_operand")]
VFMLA16_LOW))]
"TARGET_F16FML"
{
@@ -6410,11 +6410,11 @@
})
(define_expand "aarch64_fml<f16mac1>l<f16quad>_high<mode>"
- [(set (match_operand:VDQSF 0 "register_operand" "=w")
+ [(set (match_operand:VDQSF 0 "register_operand")
(unspec:VDQSF
- [(match_operand:VDQSF 1 "register_operand" "0")
- (match_operand:<VFMLA_W> 2 "register_operand" "w")
- (match_operand:<VFMLA_W> 3 "register_operand" "w")]
+ [(match_operand:VDQSF 1 "register_operand")
+ (match_operand:<VFMLA_W> 2 "register_operand")
+ (match_operand:<VFMLA_W> 3 "register_operand")]
VFMLA16_HIGH))]
"TARGET_F16FML"
{
@@ -6500,11 +6500,11 @@
)
(define_expand "aarch64_fml<f16mac1>l_lane_lowv2sf"
- [(set (match_operand:V2SF 0 "register_operand" "")
- (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "")
- (match_operand:V4HF 2 "register_operand" "")
- (match_operand:V4HF 3 "register_operand" "")
- (match_operand:SI 4 "aarch64_imm2" "")]
+ [(set (match_operand:V2SF 0 "register_operand")
+ (unspec:V2SF [(match_operand:V2SF 1 "register_operand")
+ (match_operand:V4HF 2 "register_operand")
+ (match_operand:V4HF 3 "register_operand")
+ (match_operand:SI 4 "aarch64_imm2")]
VFMLA16_LOW))]
"TARGET_F16FML"
{
@@ -6521,11 +6521,11 @@
)
(define_expand "aarch64_fml<f16mac1>l_lane_highv2sf"
- [(set (match_operand:V2SF 0 "register_operand" "")
- (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "")
- (match_operand:V4HF 2 "register_operand" "")
- (match_operand:V4HF 3 "register_operand" "")
- (match_operand:SI 4 "aarch64_imm2" "")]
+ [(set (match_operand:V2SF 0 "register_operand")
+ (unspec:V2SF [(match_operand:V2SF 1 "register_operand")
+ (match_operand:V4HF 2 "register_operand")
+ (match_operand:V4HF 3 "register_operand")
+ (match_operand:SI 4 "aarch64_imm2")]
VFMLA16_HIGH))]
"TARGET_F16FML"
{
@@ -6615,11 +6615,11 @@
)
(define_expand "aarch64_fml<f16mac1>lq_laneq_lowv4sf"
- [(set (match_operand:V4SF 0 "register_operand" "")
- (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "")
- (match_operand:V8HF 2 "register_operand" "")
- (match_operand:V8HF 3 "register_operand" "")
- (match_operand:SI 4 "aarch64_lane_imm3" "")]
+ [(set (match_operand:V4SF 0 "register_operand")
+ (unspec:V4SF [(match_operand:V4SF 1 "register_operand")
+ (match_operand:V8HF 2 "register_operand")
+ (match_operand:V8HF 3 "register_operand")
+ (match_operand:SI 4 "aarch64_lane_imm3")]
VFMLA16_LOW))]
"TARGET_F16FML"
{
@@ -6635,11 +6635,11 @@
})
(define_expand "aarch64_fml<f16mac1>lq_laneq_highv4sf"
- [(set (match_operand:V4SF 0 "register_operand" "")
- (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "")
- (match_operand:V8HF 2 "register_operand" "")
- (match_operand:V8HF 3 "register_operand" "")
- (match_operand:SI 4 "aarch64_lane_imm3" "")]
+ [(set (match_operand:V4SF 0 "register_operand")
+ (unspec:V4SF [(match_operand:V4SF 1 "register_operand")
+ (match_operand:V8HF 2 "register_operand")
+ (match_operand:V8HF 3 "register_operand")
+ (match_operand:SI 4 "aarch64_lane_imm3")]
VFMLA16_HIGH))]
"TARGET_F16FML"
{
@@ -6729,11 +6729,11 @@
)
(define_expand "aarch64_fml<f16mac1>l_laneq_lowv2sf"
- [(set (match_operand:V2SF 0 "register_operand" "")
- (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "")
- (match_operand:V4HF 2 "register_operand" "")
- (match_operand:V8HF 3 "register_operand" "")
- (match_operand:SI 4 "aarch64_lane_imm3" "")]
+ [(set (match_operand:V2SF 0 "register_operand")
+ (unspec:V2SF [(match_operand:V2SF 1 "register_operand")
+ (match_operand:V4HF 2 "register_operand")
+ (match_operand:V8HF 3 "register_operand")
+ (match_operand:SI 4 "aarch64_lane_imm3")]
VFMLA16_LOW))]
"TARGET_F16FML"
{
@@ -6750,11 +6750,11 @@
})
(define_expand "aarch64_fml<f16mac1>l_laneq_highv2sf"
- [(set (match_operand:V2SF 0 "register_operand" "")
- (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "")
- (match_operand:V4HF 2 "register_operand" "")
- (match_operand:V8HF 3 "register_operand" "")
- (match_operand:SI 4 "aarch64_lane_imm3" "")]
+ [(set (match_operand:V2SF 0 "register_operand")
+ (unspec:V2SF [(match_operand:V2SF 1 "register_operand")
+ (match_operand:V4HF 2 "register_operand")
+ (match_operand:V8HF 3 "register_operand")
+ (match_operand:SI 4 "aarch64_lane_imm3")]
VFMLA16_HIGH))]
"TARGET_F16FML"
{
@@ -6845,11 +6845,11 @@
)
(define_expand "aarch64_fml<f16mac1>lq_lane_lowv4sf"
- [(set (match_operand:V4SF 0 "register_operand" "")
- (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "")
- (match_operand:V8HF 2 "register_operand" "")
- (match_operand:V4HF 3 "register_operand" "")
- (match_operand:SI 4 "aarch64_imm2" "")]
+ [(set (match_operand:V4SF 0 "register_operand")
+ (unspec:V4SF [(match_operand:V4SF 1 "register_operand")
+ (match_operand:V8HF 2 "register_operand")
+ (match_operand:V4HF 3 "register_operand")
+ (match_operand:SI 4 "aarch64_imm2")]
VFMLA16_LOW))]
"TARGET_F16FML"
{
@@ -6865,11 +6865,11 @@
})
(define_expand "aarch64_fml<f16mac1>lq_lane_highv4sf"
- [(set (match_operand:V4SF 0 "register_operand" "")
- (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "")
- (match_operand:V8HF 2 "register_operand" "")
- (match_operand:V4HF 3 "register_operand" "")
- (match_operand:SI 4 "aarch64_imm2" "")]
+ [(set (match_operand:V4SF 0 "register_operand")
+ (unspec:V4SF [(match_operand:V4SF 1 "register_operand")
+ (match_operand:V8HF 2 "register_operand")
+ (match_operand:V4HF 3 "register_operand")
+ (match_operand:SI 4 "aarch64_imm2")]
VFMLA16_HIGH))]
"TARGET_F16FML"
{
diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index ba39134e0ae..2f757a50410 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -148,7 +148,7 @@
[(parallel
[(set (match_operand 0)
(match_operand 1))
- (clobber (match_operand:VNx16BI 2 "register_operand" "=Upl"))])]
+ (clobber (match_operand:VNx16BI 2 "register_operand"))])]
"TARGET_SVE && BYTES_BIG_ENDIAN"
{
/* Create a PTRUE. */
@@ -3204,7 +3204,7 @@
;; Standard pattern name vec_init<mode><Vel>.
(define_expand "vec_init<mode><Vel>"
- [(match_operand:SVE_ALL 0 "register_operand" "")
+ [(match_operand:SVE_ALL 0 "register_operand")
(match_operand 1 "" "")]
"TARGET_SVE"
{
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 526c7fb0dab..d1c9c8cc607 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -387,8 +387,8 @@
(define_expand "cbranch<mode>4"
[(set (pc) (if_then_else (match_operator 0 "aarch64_comparison_operator"
- [(match_operand:GPI 1 "register_operand" "")
- (match_operand:GPI 2 "aarch64_plus_operand" "")])
+ [(match_operand:GPI 1 "register_operand")
+ (match_operand:GPI 2 "aarch64_plus_operand")])
(label_ref (match_operand 3 "" ""))
(pc)))]
""
@@ -401,8 +401,8 @@
(define_expand "cbranch<mode>4"
[(set (pc) (if_then_else (match_operator 0 "aarch64_comparison_operator"
- [(match_operand:GPF 1 "register_operand" "")
- (match_operand:GPF 2 "aarch64_fp_compare_operand" "")])
+ [(match_operand:GPF 1 "register_operand")
+ (match_operand:GPF 2 "aarch64_fp_compare_operand")])
(label_ref (match_operand 3 "" ""))
(pc)))]
""
@@ -416,7 +416,7 @@
(define_expand "cbranchcc4"
[(set (pc) (if_then_else
(match_operator 0 "aarch64_comparison_operator"
- [(match_operand 1 "cc_register" "")
+ [(match_operand 1 "cc_register")
(match_operand 2 "const0_operand")])
(label_ref (match_operand 3 "" ""))
(pc)))]
@@ -479,9 +479,9 @@
;; csneg x0, x0, x1, mi
(define_expand "mod<mode>3"
- [(match_operand:GPI 0 "register_operand" "")
- (match_operand:GPI 1 "register_operand" "")
- (match_operand:GPI 2 "const_int_operand" "")]
+ [(match_operand:GPI 0 "register_operand")
+ (match_operand:GPI 1 "register_operand")
+ (match_operand:GPI 2 "const_int_operand")]
""
{
HOST_WIDE_INT val = INTVAL (operands[2]);
@@ -588,9 +588,9 @@
)
(define_expand "casesi"
- [(match_operand:SI 0 "register_operand" "") ; Index
- (match_operand:SI 1 "const_int_operand" "") ; Lower bound
- (match_operand:SI 2 "const_int_operand" "") ; Total range
+ [(match_operand:SI 0 "register_operand") ; Index
+ (match_operand:SI 1 "const_int_operand") ; Lower bound
+ (match_operand:SI 2 "const_int_operand") ; Total range
(match_operand:DI 3 "" "") ; Table label
(match_operand:DI 4 "" "")] ; Out of range label
""
@@ -876,8 +876,8 @@
;; -------------------------------------------------------------------
(define_expand "call"
- [(parallel [(call (match_operand 0 "memory_operand" "")
- (match_operand 1 "general_operand" ""))
+ [(parallel [(call (match_operand 0 "memory_operand")
+ (match_operand 1 "general_operand"))
(use (match_operand 2 "" ""))
(clobber (reg:DI LR_REGNUM))])]
""
@@ -901,8 +901,8 @@
(define_expand "call_value"
[(parallel [(set (match_operand 0 "" "")
- (call (match_operand 1 "memory_operand" "")
- (match_operand 2 "general_operand" "")))
+ (call (match_operand 1 "memory_operand")
+ (match_operand 2 "general_operand")))
(use (match_operand 3 "" ""))
(clobber (reg:DI LR_REGNUM))])]
""
@@ -926,8 +926,8 @@
)
(define_expand "sibcall"
- [(parallel [(call (match_operand 0 "memory_operand" "")
- (match_operand 1 "general_operand" ""))
+ [(parallel [(call (match_operand 0 "memory_operand")
+ (match_operand 1 "general_operand"))
(return)
(use (match_operand 2 "" ""))])]
""
@@ -939,8 +939,8 @@
(define_expand "sibcall_value"
[(parallel [(set (match_operand 0 "" "")
- (call (match_operand 1 "memory_operand" "")
- (match_operand 2 "general_operand" "")))
+ (call (match_operand 1 "memory_operand")
+ (match_operand 2 "general_operand")))
(return)
(use (match_operand 3 "" ""))])]
""
@@ -1006,8 +1006,8 @@
;; -------------------------------------------------------------------
(define_expand "mov<mode>"
- [(set (match_operand:SHORT 0 "nonimmediate_operand" "")
- (match_operand:SHORT 1 "general_operand" ""))]
+ [(set (match_operand:SHORT 0 "nonimmediate_operand")
+ (match_operand:SHORT 1 "general_operand"))]
""
"
if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
@@ -1063,8 +1063,8 @@
)
(define_expand "mov<mode>"
- [(set (match_operand:GPI 0 "nonimmediate_operand" "")
- (match_operand:GPI 1 "general_operand" ""))]
+ [(set (match_operand:GPI 0 "nonimmediate_operand")
+ (match_operand:GPI 1 "general_operand"))]
""
"
if (MEM_P (operands[0]) && CONST_INT_P (operands[1])
@@ -1170,8 +1170,8 @@
)
(define_expand "movti"
- [(set (match_operand:TI 0 "nonimmediate_operand" "")
- (match_operand:TI 1 "general_operand" ""))]
+ [(set (match_operand:TI 0 "nonimmediate_operand")
+ (match_operand:TI 1 "general_operand"))]
""
"
if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
@@ -1225,8 +1225,8 @@
})
(define_expand "mov<mode>"
- [(set (match_operand:GPF_TF_F16 0 "nonimmediate_operand" "")
- (match_operand:GPF_TF_F16 1 "general_operand" ""))]
+ [(set (match_operand:GPF_TF_F16 0 "nonimmediate_operand")
+ (match_operand:GPF_TF_F16 1 "general_operand"))]
""
{
if (!TARGET_FLOAT)
@@ -1710,9 +1710,9 @@
(define_expand "add<mode>3"
[(set
- (match_operand:GPI 0 "register_operand" "")
- (plus:GPI (match_operand:GPI 1 "register_operand" "")
- (match_operand:GPI 2 "aarch64_pluslong_or_poly_operand" "")))]
+ (match_operand:GPI 0 "register_operand")
+ (plus:GPI (match_operand:GPI 1 "register_operand")
+ (match_operand:GPI 2 "aarch64_pluslong_or_poly_operand")))]
""
{
/* If operands[1] is a subreg extract the inner RTX. */
@@ -1905,9 +1905,9 @@
})
(define_expand "addti3"
- [(set (match_operand:TI 0 "register_operand" "")
- (plus:TI (match_operand:TI 1 "register_operand" "")
- (match_operand:TI 2 "aarch64_reg_or_imm" "")))]
+ [(set (match_operand:TI 0 "register_operand")
+ (plus:TI (match_operand:TI 1 "register_operand")
+ (match_operand:TI 2 "aarch64_reg_or_imm")))]
""
{
rtx low_dest, op1_low, op2_low, high_dest, op1_high, op2_high;
@@ -1938,9 +1938,9 @@
})
(define_expand "addvti4"
- [(match_operand:TI 0 "register_operand" "")
- (match_operand:TI 1 "register_operand" "")
- (match_operand:TI 2 "aarch64_reg_or_imm" "")
+ [(match_operand:TI 0 "register_operand")
+ (match_operand:TI 1 "register_operand")
+ (match_operand:TI 2 "aarch64_reg_or_imm")
(label_ref (match_operand 3 "" ""))]
""
{
@@ -1972,9 +1972,9 @@
})
(define_expand "uaddvti4"
- [(match_operand:TI 0 "register_operand" "")
- (match_operand:TI 1 "register_operand" "")
- (match_operand:TI 2 "aarch64_reg_or_imm" "")
+ [(match_operand:TI 0 "register_operand")
+ (match_operand:TI 1 "register_operand")
+ (match_operand:TI 2 "aarch64_reg_or_imm")
(label_ref (match_operand 3 "" ""))]
""
{
@@ -2509,9 +2509,9 @@
(plus:<DWI>
(match_dup 4)
(zero_extend:<DWI>
- (match_operand:GPI 1 "register_operand" "")))
+ (match_operand:GPI 1 "register_operand")))
(zero_extend:<DWI>
- (match_operand:GPI 2 "register_operand" "")))
+ (match_operand:GPI 2 "register_operand")))
(match_dup 6)))
(set (match_operand:GPI 0 "register_operand")
(plus:GPI
@@ -2572,9 +2572,9 @@
(plus:<DWI>
(match_dup 3)
(sign_extend:<DWI>
- (match_operand:GPI 1 "register_operand" "")))
+ (match_operand:GPI 1 "register_operand")))
(sign_extend:<DWI>
- (match_operand:GPI 2 "register_operand" "")))
+ (match_operand:GPI 2 "register_operand")))
(sign_extend:<DWI>
(plus:GPI
(plus:GPI (match_dup 4) (match_dup 1))
@@ -2843,9 +2843,9 @@
})
(define_expand "subti3"
- [(set (match_operand:TI 0 "register_operand" "")
- (minus:TI (match_operand:TI 1 "aarch64_reg_or_zero" "")
- (match_operand:TI 2 "register_operand" "")))]
+ [(set (match_operand:TI 0 "register_operand")
+ (minus:TI (match_operand:TI 1 "aarch64_reg_or_zero")
+ (match_operand:TI 2 "register_operand")))]
""
{
rtx low_dest, op1_low, op2_low, high_dest, op1_high, op2_high;
@@ -3293,12 +3293,12 @@
[(set (reg:CC CC_REGNUM)
(compare:CC
(zero_extend:<DWI>
- (match_operand:GPI 1 "aarch64_reg_or_zero" ""))
+ (match_operand:GPI 1 "aarch64_reg_or_zero"))
(plus:<DWI>
(zero_extend:<DWI>
- (match_operand:GPI 2 "register_operand" ""))
+ (match_operand:GPI 2 "register_operand"))
(ltu:<DWI> (reg:CC CC_REGNUM) (const_int 0)))))
- (set (match_operand:GPI 0 "register_operand" "")
+ (set (match_operand:GPI 0 "register_operand")
(minus:GPI
(minus:GPI (match_dup 1) (match_dup 2))
(ltu:GPI (reg:CC CC_REGNUM) (const_int 0))))])]
@@ -3361,16 +3361,16 @@
(compare:CC_V
(minus:<DWI>
(sign_extend:<DWI>
- (match_operand:GPI 1 "aarch64_reg_or_zero" ""))
+ (match_operand:GPI 1 "aarch64_reg_or_zero"))
(plus:<DWI>
(sign_extend:<DWI>
- (match_operand:GPI 2 "register_operand" ""))
+ (match_operand:GPI 2 "register_operand"))
(ltu:<DWI> (reg:CC CC_REGNUM) (const_int 0))))
(sign_extend:<DWI>
(minus:GPI (match_dup 1)
(plus:GPI (ltu:GPI (reg:CC CC_REGNUM) (const_int 0))
(match_dup 2))))))
- (set (match_operand:GPI 0 "register_operand" "")
+ (set (match_operand:GPI 0 "register_operand")
(minus:GPI
(minus:GPI (match_dup 1) (match_dup 2))
(ltu:GPI (reg:CC CC_REGNUM) (const_int 0))))])]
@@ -3483,8 +3483,8 @@
)
(define_expand "abs<mode>2"
- [(match_operand:GPI 0 "register_operand" "")
- (match_operand:GPI 1 "register_operand" "")]
+ [(match_operand:GPI 0 "register_operand")
+ (match_operand:GPI 1 "register_operand")]
""
{
rtx ccreg = aarch64_gen_compare_reg (LT, operands[1], const0_rtx);
@@ -3897,10 +3897,10 @@
;; -------------------------------------------------------------------
(define_expand "cstore<mode>4"
- [(set (match_operand:SI 0 "register_operand" "")
+ [(set (match_operand:SI 0 "register_operand")
(match_operator:SI 1 "aarch64_comparison_operator"
- [(match_operand:GPI 2 "register_operand" "")
- (match_operand:GPI 3 "aarch64_plus_operand" "")]))]
+ [(match_operand:GPI 2 "register_operand")
+ (match_operand:GPI 3 "aarch64_plus_operand")]))]
""
"
operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
@@ -3922,10 +3922,10 @@
(define_expand "cstore<mode>4"
- [(set (match_operand:SI 0 "register_operand" "")
+ [(set (match_operand:SI 0 "register_operand")
(match_operator:SI 1 "aarch64_comparison_operator_mode"
- [(match_operand:GPF 2 "register_operand" "")
- (match_operand:GPF 3 "aarch64_fp_compare_operand" "")]))]
+ [(match_operand:GPF 2 "register_operand")
+ (match_operand:GPF 3 "aarch64_fp_compare_operand")]))]
""
"
operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
@@ -4010,13 +4010,13 @@
)
(define_expand "cmov<mode>6"
- [(set (match_operand:GPI 0 "register_operand" "")
+ [(set (match_operand:GPI 0 "register_operand")
(if_then_else:GPI
(match_operator 1 "aarch64_comparison_operator"
- [(match_operand:GPI 2 "register_operand" "")
- (match_operand:GPI 3 "aarch64_plus_operand" "")])
- (match_operand:GPI 4 "register_operand" "")
- (match_operand:GPI 5 "register_operand" "")))]
+ [(match_operand:GPI 2 "register_operand")
+ (match_operand:GPI 3 "aarch64_plus_operand")])
+ (match_operand:GPI 4 "register_operand")
+ (match_operand:GPI 5 "register_operand")))]
""
"
operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
@@ -4026,13 +4026,13 @@
)
(define_expand "cmov<mode>6"
- [(set (match_operand:GPF 0 "register_operand" "")
+ [(set (match_operand:GPF 0 "register_operand")
(if_then_else:GPF
(match_operator 1 "aarch64_comparison_operator"
- [(match_operand:GPF 2 "register_operand" "")
- (match_operand:GPF 3 "aarch64_fp_compare_operand" "")])
- (match_operand:GPF 4 "register_operand" "")
- (match_operand:GPF 5 "register_operand" "")))]
+ [(match_operand:GPF 2 "register_operand")
+ (match_operand:GPF 3 "aarch64_fp_compare_operand")])
+ (match_operand:GPF 4 "register_operand")
+ (match_operand:GPF 5 "register_operand")))]
""
"
operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
@@ -4110,10 +4110,10 @@
)
(define_expand "mov<mode>cc"
- [(set (match_operand:ALLI 0 "register_operand" "")
- (if_then_else:ALLI (match_operand 1 "aarch64_comparison_operator" "")
- (match_operand:ALLI 2 "register_operand" "")
- (match_operand:ALLI 3 "register_operand" "")))]
+ [(set (match_operand:ALLI 0 "register_operand")
+ (if_then_else:ALLI (match_operand 1 "aarch64_comparison_operator")
+ (match_operand:ALLI 2 "register_operand")
+ (match_operand:ALLI 3 "register_operand")))]
""
{
rtx ccreg;
@@ -4129,10 +4129,10 @@
)
(define_expand "mov<GPF:mode><GPI:mode>cc"
- [(set (match_operand:GPI 0 "register_operand" "")
- (if_then_else:GPI (match_operand 1 "aarch64_comparison_operator" "")
- (match_operand:GPF 2 "register_operand" "")
- (match_operand:GPF 3 "register_operand" "")))]
+ [(set (match_operand:GPI 0 "register_operand")
+ (if_then_else:GPI (match_operand 1 "aarch64_comparison_operator")
+ (match_operand:GPF 2 "register_operand")
+ (match_operand:GPF 3 "register_operand")))]
""
{
rtx ccreg;
@@ -4148,10 +4148,10 @@
)
(define_expand "mov<mode>cc"
- [(set (match_operand:GPF 0 "register_operand" "")
- (if_then_else:GPF (match_operand 1 "aarch64_comparison_operator" "")
- (match_operand:GPF 2 "register_operand" "")
- (match_operand:GPF 3 "register_operand" "")))]
+ [(set (match_operand:GPF 0 "register_operand")
+ (if_then_else:GPF (match_operand 1 "aarch64_comparison_operator")
+ (match_operand:GPF 2 "register_operand")
+ (match_operand:GPF 3 "register_operand")))]
""
{
rtx ccreg;
@@ -4167,10 +4167,10 @@
)
(define_expand "<neg_not_op><mode>cc"
- [(set (match_operand:GPI 0 "register_operand" "")
- (if_then_else:GPI (match_operand 1 "aarch64_comparison_operator" "")
- (NEG_NOT:GPI (match_operand:GPI 2 "register_operand" ""))
- (match_operand:GPI 3 "register_operand" "")))]
+ [(set (match_operand:GPI 0 "register_operand")
+ (if_then_else:GPI (match_operand 1 "aarch64_comparison_operator")
+ (NEG_NOT:GPI (match_operand:GPI 2 "register_operand"))
+ (match_operand:GPI 3 "register_operand")))]
""
{
rtx ccreg;
@@ -5399,7 +5399,7 @@
;; -------------------------------------------------------------------
(define_expand "<optab>"
- [(set (match_operand:DI 0 "register_operand" "=r")
+ [(set (match_operand:DI 0 "register_operand")
(ANY_EXTRACT:DI (match_operand:DI 1 "register_operand")
(match_operand 2
"aarch64_simd_shift_imm_offset_di")
@@ -6249,8 +6249,8 @@
)
(define_expand "sqrt<mode>2"
- [(set (match_operand:GPF_F16 0 "register_operand" "=w")
- (sqrt:GPF_F16 (match_operand:GPF_F16 1 "register_operand" "w")))]
+ [(set (match_operand:GPF_F16 0 "register_operand")
+ (sqrt:GPF_F16 (match_operand:GPF_F16 1 "register_operand")))]
"TARGET_FLOAT"
{
if (aarch64_emit_approx_sqrt (operands[0], operands[1], false))
@@ -6410,9 +6410,9 @@
;; Reload Scalar Floating point modes from constant pool.
;; The AArch64 port doesn't have __int128 constant move support.
(define_expand "@aarch64_reload_movcp<GPF_TF:mode><P:mode>"
- [(set (match_operand:GPF_TF 0 "register_operand" "=w")
- (mem:GPF_TF (match_operand 1 "aarch64_constant_pool_symref" "S")))
- (clobber (match_operand:P 2 "register_operand" "=&r"))]
+ [(set (match_operand:GPF_TF 0 "register_operand")
+ (mem:GPF_TF (match_operand 1 "aarch64_constant_pool_symref")))
+ (clobber (match_operand:P 2 "register_operand"))]
"TARGET_FLOAT"
{
aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
@@ -6423,9 +6423,9 @@
;; Reload Vector modes from constant pool.
(define_expand "@aarch64_reload_movcp<VALL:mode><P:mode>"
- [(set (match_operand:VALL 0 "register_operand" "=w")
- (mem:VALL (match_operand 1 "aarch64_constant_pool_symref" "S")))
- (clobber (match_operand:P 2 "register_operand" "=&r"))]
+ [(set (match_operand:VALL 0 "register_operand")
+ (mem:VALL (match_operand 1 "aarch64_constant_pool_symref")))
+ (clobber (match_operand:P 2 "register_operand"))]
"TARGET_FLOAT"
{
aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
@@ -6435,9 +6435,9 @@
)
(define_expand "@aarch64_reload_mov<mode>"
- [(set (match_operand:TX 0 "register_operand" "=w")
- (match_operand:TX 1 "register_operand" "w"))
- (clobber (match_operand:DI 2 "register_operand" "=&r"))
+ [(set (match_operand:TX 0 "register_operand")
+ (match_operand:TX 1 "register_operand"))
+ (clobber (match_operand:DI 2 "register_operand"))
]
"TARGET_FLOAT"
{
@@ -6509,9 +6509,9 @@
;; rodata section.
(define_expand "add_losym"
- [(set (match_operand 0 "register_operand" "=r")
- (lo_sum (match_operand 1 "register_operand" "r")
- (match_operand 2 "aarch64_valid_symref" "S")))]
+ [(set (match_operand 0 "register_operand")
+ (lo_sum (match_operand 1 "register_operand")
+ (match_operand 2 "aarch64_valid_symref")))]
""
{
machine_mode mode = GET_MODE (operands[0]);
@@ -6600,9 +6600,9 @@
;; instructions in the TLS stubs, in order to enable linker relaxation.
;; Therefore we treat the stubs as an atomic sequence.
(define_expand "tlsgd_small_<mode>"
- [(parallel [(set (match_operand 0 "register_operand" "")
+ [(parallel [(set (match_operand 0 "register_operand")
(call (mem:DI (match_dup 2)) (const_int 1)))
- (unspec:DI [(match_operand:PTR 1 "aarch64_valid_symref" "")] UNSPEC_GOTSMALLTLS)
+ (unspec:DI [(match_operand:PTR 1 "aarch64_valid_symref")] UNSPEC_GOTSMALLTLS)
(clobber (reg:DI LR_REGNUM))])]
""
{
@@ -6883,7 +6883,7 @@
;; Named pattern for expanding thread pointer reference.
(define_expand "get_thread_pointerdi"
- [(match_operand:DI 0 "register_operand" "=r")]
+ [(match_operand:DI 0 "register_operand")]
""
{
rtx tmp = aarch64_load_tp (operands[0]);
@@ -7140,10 +7140,10 @@
;; tracking enabled. Use the speculation tracker to decide whether to
;; copy operand 1 to the target, or to copy the fail value (operand 2).
(define_expand "@despeculate_copy<ALLI_TI:mode>"
- [(set (match_operand:ALLI_TI 0 "register_operand" "=r")
+ [(set (match_operand:ALLI_TI 0 "register_operand")
(unspec_volatile:ALLI_TI
- [(match_operand:ALLI_TI 1 "register_operand" "r")
- (match_operand:ALLI_TI 2 "aarch64_reg_or_zero" "rZ")
+ [(match_operand:ALLI_TI 1 "register_operand")
+ (match_operand:ALLI_TI 2 "aarch64_reg_or_zero")
(use (reg:DI SPECULATION_TRACKER_REGNUM))
(clobber (reg:CC CC_REGNUM))] UNSPECV_SPECULATION_BARRIER))]
""
diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md
index b6b5f6be232..a679270cd38 100644
--- a/gcc/config/aarch64/atomics.md
+++ b/gcc/config/aarch64/atomics.md
@@ -21,11 +21,11 @@
;; Instruction patterns.
(define_expand "@atomic_compare_and_swap<mode>"
- [(match_operand:SI 0 "register_operand" "") ;; bool out
- (match_operand:ALLI 1 "register_operand" "") ;; val out
- (match_operand:ALLI 2 "aarch64_sync_memory_operand" "") ;; memory
- (match_operand:ALLI 3 "nonmemory_operand" "") ;; expected
- (match_operand:ALLI 4 "aarch64_reg_or_zero" "") ;; desired
+ [(match_operand:SI 0 "register_operand") ;; bool out
+ (match_operand:ALLI 1 "register_operand") ;; val out
+ (match_operand:ALLI 2 "aarch64_sync_memory_operand") ;; memory
+ (match_operand:ALLI 3 "nonmemory_operand") ;; expected
+ (match_operand:ALLI 4 "aarch64_reg_or_zero") ;; desired
(match_operand:SI 5 "const_int_operand") ;; is_weak
(match_operand:SI 6 "const_int_operand") ;; mod_s
(match_operand:SI 7 "const_int_operand")] ;; mod_f
@@ -134,10 +134,10 @@
})
(define_expand "atomic_exchange<mode>"
- [(match_operand:ALLI 0 "register_operand" "")
- (match_operand:ALLI 1 "aarch64_sync_memory_operand" "")
- (match_operand:ALLI 2 "aarch64_reg_or_zero" "")
- (match_operand:SI 3 "const_int_operand" "")]
+ [(match_operand:ALLI 0 "register_operand")
+ (match_operand:ALLI 1 "aarch64_sync_memory_operand")
+ (match_operand:ALLI 2 "aarch64_reg_or_zero")
+ (match_operand:SI 3 "const_int_operand")]
""
{
rtx (*gen) (rtx, rtx, rtx, rtx);
@@ -198,9 +198,9 @@
)
(define_expand "atomic_<atomic_optab><mode>"
- [(match_operand:ALLI 0 "aarch64_sync_memory_operand" "")
+ [(match_operand:ALLI 0 "aarch64_sync_memory_operand")
(atomic_op:ALLI
- (match_operand:ALLI 1 "<atomic_op_operand>" "")
+ (match_operand:ALLI 1 "<atomic_op_operand>")
(match_operand:SI 2 "const_int_operand"))]
""
{
@@ -322,10 +322,10 @@
;; Load-operate-store, returning the original memory data.
(define_expand "atomic_fetch_<atomic_optab><mode>"
- [(match_operand:ALLI 0 "register_operand" "")
- (match_operand:ALLI 1 "aarch64_sync_memory_operand" "")
+ [(match_operand:ALLI 0 "register_operand")
+ (match_operand:ALLI 1 "aarch64_sync_memory_operand")
(atomic_op:ALLI
- (match_operand:ALLI 2 "<atomic_op_operand>" "")
+ (match_operand:ALLI 2 "<atomic_op_operand>")
(match_operand:SI 3 "const_int_operand"))]
""
{
@@ -439,10 +439,10 @@
;; Load-operate-store, returning the updated memory data.
(define_expand "atomic_<atomic_optab>_fetch<mode>"
- [(match_operand:ALLI 0 "register_operand" "")
+ [(match_operand:ALLI 0 "register_operand")
(atomic_op:ALLI
- (match_operand:ALLI 1 "aarch64_sync_memory_operand" "")
- (match_operand:ALLI 2 "<atomic_op_operand>" ""))
+ (match_operand:ALLI 1 "aarch64_sync_memory_operand")
+ (match_operand:ALLI 2 "<atomic_op_operand>"))
(match_operand:SI 3 "const_int_operand")]
""
{
@@ -600,7 +600,7 @@
)
(define_expand "mem_thread_fence"
- [(match_operand:SI 0 "const_int_operand" "")]
+ [(match_operand:SI 0 "const_int_operand")]
""
{
enum memmodel model = memmodel_from_int (INTVAL (operands[0]));
