On Wed, Aug 07, 2019 at 07:19:12PM +0100, Richard Sandiford wrote: > Some indexed SVE FCMLA operations have a 3-bit register field that > requires one of Z0-Z7. This patch adds a public "y" constraint for that. > > The patch also documents "x", which is again intended to be a public > constraint. > > Tested on aarch64-linux-gnu (with and without SVE) and aarch64_be-elf. > OK to install?
I had the vague recollection that 'y' already meant something... I'm guessing you already checked, but just in case, please check. Otherwise, this is OK. Thanks, James > > Richard > > > 2019-08-07 Richard Sandiford <richard.sandif...@arm.com> > > gcc/ > * doc/md.texi: Document the x and y constraints for AArch64. > * config/aarch64/aarch64.h (FP_LO8_REGNUM_P): New macro. > (FP_LO8_REGS): New reg_class. > (REG_CLASS_NAMES, REG_CLASS_CONTENTS): Add an entry for FP_LO8_REGS. > * config/aarch64/aarch64.c (aarch64_hard_regno_nregs) > (aarch64_regno_regclass, aarch64_class_max_nregs): Handle FP_LO8_REGS. > * config/aarch64/predicates.md (aarch64_simd_register): Use > FP_REGNUM_P instead of checking the classes manually. > * config/aarch64/constraints.md (y): New constraint. > > gcc/testsuite/ > * gcc.target/aarch64/asm-x-constraint-1.c: New test. > * gcc.target/aarch64/asm-y-constraint-1.c: Likewise. >
