I was asked to split V4 patch #4.2 into smaller chuncks. This patch is one of 8 patches that were broken out from 4.2. Another patch from 4.2 to use SIGNED_16BIT_OFFSET_EXTRA_P has already been committed.
This patch sets the prefixed and non-prefixed instruction sizes for the non-vector 128-bit mode (PTImode, TDmode, IFmode, and optionally TFmode). Using all of the patches in this series, I have bootstrapped the compiler on a little endian power8 system and ran the regression tests. In addition, I have built the Spec 2006 and 2017 benchmark suites, for -mcpu=power8, -mcpu=power9, and -mcpu=future, and all of the benchmarks build. Can I check this into the trunk? 2019-10-03 Michael Meissner <meiss...@linux.ibm.com> * config/rs6000/rs6000.md (mov<mode>_64bit_dm): Set prefixed and non-prefixed length. (movtd_64bit_nodm): Set prefixed and non-prefixed length. (mov<mode>_ppc64): Set prefixed and non-prefixed length. Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md (revision 276534) +++ gcc/config/rs6000/rs6000.md (working copy) @@ -7773,9 +7773,13 @@ (define_insn_and_split "*mov<mode>_64bit "#" "&& reload_completed" [(pc)] -{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; } - [(set_attr "length" "8") - (set_attr "isa" "*,*,*,*,*,*,*,*,p8v,p8v")]) +{ + rs6000_split_multireg_move (operands[0], operands[1]); + DONE; +} + [(set_attr "isa" "*,*,*,*,*,*,*,*,p8v,p8v") + (set_attr "non_prefixed_length" "8") + (set_attr "prefixed_length" "20")]) (define_insn_and_split "*movtd_64bit_nodm" [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r") @@ -7786,8 +7790,12 @@ (define_insn_and_split "*movtd_64bit_nod "#" "&& reload_completed" [(pc)] -{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; } - [(set_attr "length" "8,8,8,12,12,8")]) +{ + rs6000_split_multireg_move (operands[0], operands[1]); + DONE; +} + [(set_attr "non_prefixed_length" "8") + (set_attr "prefixed_length" "20")]) (define_insn_and_split "*mov<mode>_32bit" [(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand" "=m,d,d,d,Y,r,r") @@ -8984,7 +8992,8 @@ (define_insn "*mov<mode>_ppc64" return rs6000_output_move_128bit (operands); } [(set_attr "type" "store,store,load,load,*,*") - (set_attr "length" "8")]) + (set_attr "prefixed_length" "20") + (set_attr "non_prefixed_length" "8")]) (define_split [(set (match_operand:TI2 0 "int_reg_operand") -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.ibm.com, phone: +1 (978) 899-4797