Hi Richard, On 29.11.19 13:37, Richard Biener wrote: > On Fri, Nov 29, 2019 at 1:24 PM Harwath, Frederik > <frede...@codesourcery.com> wrote: > [...] >> It seems that this rule is not invoked when compiling for x86_64 where the >> generated code for vect-cond-reduc-1.c does not contain anything that would >> match this rule. Could it be that there is no test covering this rule for >> commonly tested architectures? > > This was all added for aarch64 SVE. So it looks like the outer plus > was conditional and we end up inheriting the I should have mentioned this, it was indeed a COND_ADD.
> condition for the inner vec_cond. Your fix looks reasonable but is > very badly formatted. Can you instead do > > if (op_Code == cOND_EPXR || op_code == vEC_COND_EXPR) > op_could_trap = generic_expr_could_trap (..) > else > op_could_trap = operation_could_trap_p (... > Sorry, sure! Thanks, Frederik
