On Wed, Dec 04, 2019 at 07:43:30PM +0900, Oleg Endo wrote: > On Tue, 2019-12-03 at 12:05 -0600, Segher Boessenkool wrote: > > > Hmm ... the R0 problem ... SH doesn't override class_likely_spilled > > > explicitly, but it's got a R0_REGS class with only one said reg in it. > > > So the default impl of class_likely_spilled should do its thing. > > > > Yes, good point. So what happened here? > > "Something, somewhere, went terribly wrong"... > > insn 18 wants to do > > mov.l @(r4,r6),r0 > > But it can't because the reg+reg address mode has a R0 constraint > itself. So it needs to be changed to > > mov r4,r0 > mov.l @(r0,r6),r0 > > And it can't handle that. Or only sometimes? Don't remember. > > > Is it just RA messing things > > up, unrelated to the new pass? > > Yep, I think so. The additional pass seems to create "tougher" code so > reload passes out earlier than usual. We've had the same issue when > trying address mode selection optimization. In fact that was one huge > showstopper.
So maybe you should have a define_insn_and_split that allows any two regs and replaces one by r0 if neither is (and a move to r0 before the load)? Split after reload of course. It may be admitting defeat, but it may even result in better code as well ;-) Segher