Hi there,
I suggest this patch to allow architectures do substitute cc0_rtx with a
generated cc register.
Why? If you are using a cc register plus your architecture as many
instructions which may clobber that cc register, some passes (e.g. gcse)
will reorder the insns. This can lead to the situation that an insn is
moved between a compare and it' consuming jump insn. Which yields
invalid code. (Note that at these stages clobbers are not yet tracked as
CLOBBER insns).
To get around this behaviour you have to fake HAVE_CC0, e.g. by adding
some dummy code to your md file:
(define_peephole2 [(set (match_operand 0 "" "") (cc0))] ""
[(const_int 0)] "")
plus some empty macros. All of this can be handled by the arch
implementation, but not the check for the cc0 inside of
int sets_cc0_p(const_rtx x)
Changelog
gcc/jump.c: use rtx_equal do determine the identity of cc0_rtx
======
--- a/gcc/jump.c
+++ b/gcc/jump.c
@@ -1028,7 +1028,7 @@ sets_cc0_p (const_rtx x)
if (INSN_P (x))
x = PATTERN (x);
- if (GET_CODE (x) == SET && SET_DEST (x) == cc0_rtx)
+ if (GET_CODE (x) == SET && rtx_equal_p(SET_DEST (x), cc0_rtx))
return 1;
if (GET_CODE (x) == PARALLEL)
{
