Random spotting. Exposes the missed benefit for delay-slot
filling of a splitter for indexed addressing mode (the [rN+M]
one). To be considered for common instructions and perhaps only
for suitable M; at least +-63 is obious (when there's a register
available) as both the original and the add fit in delay-slots.
I forgot to mention that all previously posted patches have been
regression-tested for cris-elf and all are committed.
---
gcc/testsuite/gcc.target/cris/dbr-1.c | 11 +++++++++++
1 file changed, 11 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/cris/dbr-1.c
diff --git a/gcc/testsuite/gcc.target/cris/dbr-1.c
b/gcc/testsuite/gcc.target/cris/dbr-1.c
new file mode 100644
index 000000000..9f79a7627
--- /dev/null
+++ b/gcc/testsuite/gcc.target/cris/dbr-1.c
@@ -0,0 +1,11 @@
+/* Check that delayed-branch-slot is able to fill a trivially fillable
+ slot. The xfail is due to the "move.d [$r10+4],$r10" not being split
+ up into "addq 4,$r10" and "move.d [$r10],$r10"; both slottable and of
+ the same actual cost in size and cycles as the unsplit insn. */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "\tnop" { xfail *-*-* } } } */
+void *f(void **p)
+{
+ return p[1];
+}
--
2.11.0
brgds, H-P
