For operands with an identical set of alternatives there is no point
in marking them commutative. This patch removes the superfluous
constraint modifiers in vector.md and vx-builtins.md since it might
slow down reload without buying us anything.
There were even two patterns where the constraint modifier was plain
wrong: "sub<VF_HW>3" and "ior_not<VT>3". Fortunately it never had any effect.
Bootstrapped and regression tested on s390x.
SPEC binaries built with and without the patch are identical.
gcc/ChangeLog:
2020-04-02 Andreas Krebbel <kreb...@linux.ibm.com>
* config/s390/vector.md ("<ti*>add<mode>3", "mul<mode>3")
("and<mode>3", "notand<mode>3", "ior<mode>3", "ior_not<mode>3")
("xor<mode>3", "notxor<mode>3", "smin<mode>3", "smax<mode>3")
("umin<mode>3", "umax<mode>3", "vec_widen_smult_even_<mode>")
("vec_widen_umult_even_<mode>", "vec_widen_smult_odd_<mode>")
("vec_widen_umult_odd_<mode>", "add<mode>3", "sub<mode>3")
("mul<mode>3", "fma<mode>4", "fms<mode>4", "neg_fma<mode>4")
("neg_fms<mode>4", "*smax<mode>3_vxe", "*smaxv2df3_vx")
("*smin<mode>3_vxe", "*sminv2df3_vx"): Remove % constraint
modifier.
("vec_widen_umult_lo_<mode>", "vec_widen_umult_hi_<mode>")
("vec_widen_smult_lo_<mode>", "vec_widen_smult_hi_<mode>"):
Remove constraints from expander.
* config/s390/vx-builtins.md ("vacc<bhfgq>_<mode>", "vacq")
("vacccq", "vec_avg<mode>", "vec_avgu<mode>", "vec_vmal<mode>")
("vec_vmah<mode>", "vec_vmalh<mode>", "vec_vmae<mode>")
("vec_vmale<mode>", "vec_vmao<mode>", "vec_vmalo<mode>")
("vec_smulh<mode>", "vec_umulh<mode>", "vec_nor<mode>3")
("vfmin<mode>", "vfmax<mode>"): Remove % constraint modifier.
---
gcc/ChangeLog | 22 ++++++++++
gcc/config/s390/vector.md | 80 +++++++++++++++++-----------------
gcc/config/s390/vx-builtins.md | 78 ++++++++++++++++-----------------
3 files changed, 101 insertions(+), 79 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 66a118b6f5f..5a8a2c525c9 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,25 @@
+2020-04-02 Andreas Krebbel <kreb...@linux.ibm.com>
+
+ * config/s390/vector.md ("<ti*>add<mode>3", "mul<mode>3")
+ ("and<mode>3", "notand<mode>3", "ior<mode>3", "ior_not<mode>3")
+ ("xor<mode>3", "notxor<mode>3", "smin<mode>3", "smax<mode>3")
+ ("umin<mode>3", "umax<mode>3", "vec_widen_smult_even_<mode>")
+ ("vec_widen_umult_even_<mode>", "vec_widen_smult_odd_<mode>")
+ ("vec_widen_umult_odd_<mode>", "add<mode>3", "sub<mode>3")
+ ("mul<mode>3", "fma<mode>4", "fms<mode>4", "neg_fma<mode>4")
+ ("neg_fms<mode>4", "*smax<mode>3_vxe", "*smaxv2df3_vx")
+ ("*smin<mode>3_vxe", "*sminv2df3_vx"): Remove % constraint
+ modifier.
+ ("vec_widen_umult_lo_<mode>", "vec_widen_umult_hi_<mode>")
+ ("vec_widen_smult_lo_<mode>", "vec_widen_smult_hi_<mode>"):
+ Remove constraints from expander.
+ * config/s390/vx-builtins.md ("vacc<bhfgq>_<mode>", "vacq")
+ ("vacccq", "vec_avg<mode>", "vec_avgu<mode>", "vec_vmal<mode>")
+ ("vec_vmah<mode>", "vec_vmalh<mode>", "vec_vmae<mode>")
+ ("vec_vmale<mode>", "vec_vmao<mode>", "vec_vmalo<mode>")
+ ("vec_smulh<mode>", "vec_umulh<mode>", "vec_nor<mode>3")
+ ("vfmin<mode>", "vfmax<mode>"): Remove % constraint modifier.
+
2020-04-01 Peter Bergner <berg...@linux.ibm.com>
PR rtl-optimization/94123
diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index 378c9e3c7fb..9d3df9813c9 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -694,7 +694,7 @@
; operation into two DImode ADDs.
(define_insn "<ti*>add<mode>3"
[(set (match_operand:VIT 0 "nonimmediate_operand" "=v")
- (plus:VIT (match_operand:VIT 1 "nonimmediate_operand" "%v")
+ (plus:VIT (match_operand:VIT 1 "nonimmediate_operand" "v")
(match_operand:VIT 2 "general_operand" "v")))]
"TARGET_VX"
"va<bhfgq>\t%v0,%v1,%v2"
@@ -704,7 +704,7 @@
(define_insn "<ti*>sub<mode>3"
[(set (match_operand:VIT 0 "nonimmediate_operand" "=v")
(minus:VIT (match_operand:VIT 1 "nonimmediate_operand" "v")
- (match_operand:VIT 2 "general_operand" "v")))]
+ (match_operand:VIT 2 "general_operand" "v")))]
"TARGET_VX"
"vs<bhfgq>\t%v0,%v1,%v2"
[(set_attr "op_type" "VRR")])
@@ -712,7 +712,7 @@
; vmlb, vmlhw, vmlf
(define_insn "mul<mode>3"
[(set (match_operand:VI_QHS 0 "register_operand" "=v")
- (mult:VI_QHS (match_operand:VI_QHS 1 "register_operand" "%v")
+ (mult:VI_QHS (match_operand:VI_QHS 1 "register_operand" "v")
(match_operand:VI_QHS 2 "register_operand" "v")))]
"TARGET_VX"
"vml<bhfgq><w>\t%v0,%v1,%v2"
@@ -767,7 +767,7 @@
(define_insn "and<mode>3"
[(set (match_operand:VT 0 "register_operand" "=v")
- (and:VT (match_operand:VT 1 "register_operand" "%v")
+ (and:VT (match_operand:VT 1 "register_operand" "v")
(match_operand:VT 2 "register_operand" "v")))]
"TARGET_VX"
"vn\t%v0,%v1,%v2"
@@ -777,7 +777,7 @@
(define_insn "notand<mode>3"
[(set (match_operand:VT 0 "register_operand" "=v")
- (ior:VT (not:VT (match_operand:VT 1 "register_operand" "%v"))
+ (ior:VT (not:VT (match_operand:VT 1 "register_operand" "v"))
(not:VT (match_operand:VT 2 "register_operand" "v"))))]
"TARGET_VXE"
"vnn\t%v0,%v1,%v2"
@@ -787,7 +787,7 @@
(define_insn "ior<mode>3"
[(set (match_operand:VT 0 "register_operand" "=v")
- (ior:VT (match_operand:VT 1 "register_operand" "%v")
+ (ior:VT (match_operand:VT 1 "register_operand" "v")
(match_operand:VT 2 "register_operand" "v")))]
"TARGET_VX"
"vo\t%v0,%v1,%v2"
@@ -798,7 +798,7 @@
(define_insn "ior_not<mode>3"
[(set (match_operand:VT 0 "register_operand" "=v")
(ior:VT (not:VT (match_operand:VT 2 "register_operand" "v"))
- (match_operand:VT 1 "register_operand" "%v")))]
+ (match_operand:VT 1 "register_operand" "v")))]
"TARGET_VXE"
"voc\t%v0,%v1,%v2"
[(set_attr "op_type" "VRR")])
@@ -807,7 +807,7 @@
(define_insn "xor<mode>3"
[(set (match_operand:VT 0 "register_operand" "=v")
- (xor:VT (match_operand:VT 1 "register_operand" "%v")
+ (xor:VT (match_operand:VT 1 "register_operand" "v")
(match_operand:VT 2 "register_operand" "v")))]
"TARGET_VX"
"vx\t%v0,%v1,%v2"
@@ -817,7 +817,7 @@
(define_insn "notxor<mode>3"
[(set (match_operand:VT 0 "register_operand" "=v")
- (not:VT (xor:VT (match_operand:VT 1 "register_operand" "%v")
+ (not:VT (xor:VT (match_operand:VT 1 "register_operand" "v")
(match_operand:VT 2 "register_operand" "v"))))]
"TARGET_VXE"
"vnx\t%v0,%v1,%v2"
@@ -1075,7 +1075,7 @@
; vmnb, vmnh, vmnf, vmng
(define_insn "smin<mode>3"
[(set (match_operand:VI 0 "register_operand" "=v")
- (smin:VI (match_operand:VI 1 "register_operand" "%v")
+ (smin:VI (match_operand:VI 1 "register_operand" "v")
(match_operand:VI 2 "register_operand" "v")))]
"TARGET_VX"
"vmn<bhfgq>\t%v0,%v1,%v2"
@@ -1084,7 +1084,7 @@
; vmxb, vmxh, vmxf, vmxg
(define_insn "smax<mode>3"
[(set (match_operand:VI 0 "register_operand" "=v")
- (smax:VI (match_operand:VI 1 "register_operand" "%v")
+ (smax:VI (match_operand:VI 1 "register_operand" "v")
(match_operand:VI 2 "register_operand" "v")))]
"TARGET_VX"
"vmx<bhfgq>\t%v0,%v1,%v2"
@@ -1093,7 +1093,7 @@
; vmnlb, vmnlh, vmnlf, vmnlg
(define_insn "umin<mode>3"
[(set (match_operand:VI 0 "register_operand" "=v")
- (umin:VI (match_operand:VI 1 "register_operand" "%v")
+ (umin:VI (match_operand:VI 1 "register_operand" "v")
(match_operand:VI 2 "register_operand" "v")))]
"TARGET_VX"
"vmnl<bhfgq>\t%v0,%v1,%v2"
@@ -1102,7 +1102,7 @@
; vmxlb, vmxlh, vmxlf, vmxlg
(define_insn "umax<mode>3"
[(set (match_operand:VI 0 "register_operand" "=v")
- (umax:VI (match_operand:VI 1 "register_operand" "%v")
+ (umax:VI (match_operand:VI 1 "register_operand" "v")
(match_operand:VI 2 "register_operand" "v")))]
"TARGET_VX"
"vmxl<bhfgq>\t%v0,%v1,%v2"
@@ -1111,7 +1111,7 @@
; vmeb, vmeh, vmef
(define_insn "vec_widen_smult_even_<mode>"
[(set (match_operand:<vec_double> 0 "register_operand" "=v")
- (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "%v")
+ (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "v")
(match_operand:VI_QHS 2 "register_operand" "v")]
UNSPEC_VEC_SMULT_EVEN))]
"TARGET_VX"
@@ -1121,7 +1121,7 @@
; vmleb, vmleh, vmlef
(define_insn "vec_widen_umult_even_<mode>"
[(set (match_operand:<vec_double> 0 "register_operand" "=v")
- (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "%v")
+ (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "v")
(match_operand:VI_QHS 2 "register_operand" "v")]
UNSPEC_VEC_UMULT_EVEN))]
"TARGET_VX"
@@ -1131,7 +1131,7 @@
; vmob, vmoh, vmof
(define_insn "vec_widen_smult_odd_<mode>"
[(set (match_operand:<vec_double> 0 "register_operand" "=v")
- (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "%v")
+ (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "v")
(match_operand:VI_QHS 2 "register_operand" "v")]
UNSPEC_VEC_SMULT_ODD))]
"TARGET_VX"
@@ -1141,7 +1141,7 @@
; vmlob, vmloh, vmlof
(define_insn "vec_widen_umult_odd_<mode>"
[(set (match_operand:<vec_double> 0 "register_operand" "=v")
- (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "%v")
+ (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "v")
(match_operand:VI_QHS 2 "register_operand" "v")]
UNSPEC_VEC_UMULT_ODD))]
"TARGET_VX"
@@ -1162,13 +1162,13 @@
(define_expand "vec_widen_umult_lo_<mode>"
[(set (match_dup 3)
- (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "%v")
- (match_operand:VI_QHS 2 "register_operand" "v")]
+ (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "")
+ (match_operand:VI_QHS 2 "register_operand" "")]
UNSPEC_VEC_UMULT_EVEN))
(set (match_dup 4)
(unspec:<vec_double> [(match_dup 1) (match_dup 2)]
UNSPEC_VEC_UMULT_ODD))
- (set (match_operand:<vec_double> 0 "register_operand" "=v")
+ (set (match_operand:<vec_double> 0 "register_operand" "")
(unspec:<vec_double> [(match_dup 3) (match_dup 4)]
UNSPEC_VEC_MERGEL))]
"TARGET_VX"
@@ -1179,13 +1179,13 @@
(define_expand "vec_widen_umult_hi_<mode>"
[(set (match_dup 3)
- (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "%v")
- (match_operand:VI_QHS 2 "register_operand" "v")]
+ (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "")
+ (match_operand:VI_QHS 2 "register_operand" "")]
UNSPEC_VEC_UMULT_EVEN))
(set (match_dup 4)
(unspec:<vec_double> [(match_dup 1) (match_dup 2)]
UNSPEC_VEC_UMULT_ODD))
- (set (match_operand:<vec_double> 0 "register_operand" "=v")
+ (set (match_operand:<vec_double> 0 "register_operand" "")
(unspec:<vec_double> [(match_dup 3) (match_dup 4)]
UNSPEC_VEC_MERGEH))]
"TARGET_VX"
@@ -1196,13 +1196,13 @@
(define_expand "vec_widen_smult_lo_<mode>"
[(set (match_dup 3)
- (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "%v")
- (match_operand:VI_QHS 2 "register_operand" "v")]
+ (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "")
+ (match_operand:VI_QHS 2 "register_operand" "")]
UNSPEC_VEC_SMULT_EVEN))
(set (match_dup 4)
(unspec:<vec_double> [(match_dup 1) (match_dup 2)]
UNSPEC_VEC_SMULT_ODD))
- (set (match_operand:<vec_double> 0 "register_operand" "=v")
+ (set (match_operand:<vec_double> 0 "register_operand" "")
(unspec:<vec_double> [(match_dup 3) (match_dup 4)]
UNSPEC_VEC_MERGEL))]
"TARGET_VX"
@@ -1213,13 +1213,13 @@
(define_expand "vec_widen_smult_hi_<mode>"
[(set (match_dup 3)
- (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "%v")
- (match_operand:VI_QHS 2 "register_operand" "v")]
+ (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "")
+ (match_operand:VI_QHS 2 "register_operand" "")]
UNSPEC_VEC_SMULT_EVEN))
(set (match_dup 4)
(unspec:<vec_double> [(match_dup 1) (match_dup 2)]
UNSPEC_VEC_SMULT_ODD))
- (set (match_operand:<vec_double> 0 "register_operand" "=v")
+ (set (match_operand:<vec_double> 0 "register_operand" "")
(unspec:<vec_double> [(match_dup 3) (match_dup 4)]
UNSPEC_VEC_MERGEH))]
"TARGET_VX"
@@ -1240,7 +1240,7 @@
; vfasb, vfadb, wfasb, wfadb, wfaxb
(define_insn "add<mode>3"
[(set (match_operand:VF_HW 0 "register_operand" "=v")
- (plus:VF_HW (match_operand:VF_HW 1 "register_operand" "%v")
+ (plus:VF_HW (match_operand:VF_HW 1 "register_operand" "v")
(match_operand:VF_HW 2 "register_operand" "v")))]
"TARGET_VX"
"<vw>fa<sdx>b\t%v0,%v1,%v2"
@@ -1249,7 +1249,7 @@
; vfssb, vfsdb, wfssb, wfsdb, wfsxb
(define_insn "sub<mode>3"
[(set (match_operand:VF_HW 0 "register_operand" "=v")
- (minus:VF_HW (match_operand:VF_HW 1 "register_operand" "%v")
+ (minus:VF_HW (match_operand:VF_HW 1 "register_operand" "v")
(match_operand:VF_HW 2 "register_operand" "v")))]
"TARGET_VX"
"<vw>fs<sdx>b\t%v0,%v1,%v2"
@@ -1258,7 +1258,7 @@
; vfmsb, vfmdb, wfmsb, wfmdb, wfmxb
(define_insn "mul<mode>3"
[(set (match_operand:VF_HW 0 "register_operand" "=v")
- (mult:VF_HW (match_operand:VF_HW 1 "register_operand" "%v")
+ (mult:VF_HW (match_operand:VF_HW 1 "register_operand" "v")
(match_operand:VF_HW 2 "register_operand" "v")))]
"TARGET_VX"
"<vw>fm<sdx>b\t%v0,%v1,%v2"
@@ -1284,7 +1284,7 @@
; vfmasb, vfmadb, wfmasb, wfmadb, wfmaxb
(define_insn "fma<mode>4"
[(set (match_operand:VF_HW 0 "register_operand" "=v")
- (fma:VF_HW (match_operand:VF_HW 1 "register_operand" "%v")
+ (fma:VF_HW (match_operand:VF_HW 1 "register_operand" "v")
(match_operand:VF_HW 2 "register_operand" "v")
(match_operand:VF_HW 3 "register_operand" "v")))]
"TARGET_VX"
@@ -1294,7 +1294,7 @@
; vfmssb, vfmsdb, wfmssb, wfmsdb, wfmsxb
(define_insn "fms<mode>4"
[(set (match_operand:VF_HW 0 "register_operand" "=v")
- (fma:VF_HW (match_operand:VF_HW 1 "register_operand" "%v")
+ (fma:VF_HW (match_operand:VF_HW 1 "register_operand" "v")
(match_operand:VF_HW 2 "register_operand" "v")
(neg:VF_HW (match_operand:VF_HW 3 "register_operand" "v"))))]
"TARGET_VX"
@@ -1305,7 +1305,7 @@
(define_insn "neg_fma<mode>4"
[(set (match_operand:VF_HW 0 "register_operand" "=v")
(neg:VF_HW
- (fma:VF_HW (match_operand:VF_HW 1 "register_operand" "%v")
+ (fma:VF_HW (match_operand:VF_HW 1 "register_operand" "v")
(match_operand:VF_HW 2 "register_operand" "v")
(match_operand:VF_HW 3 "register_operand" "v"))))]
"TARGET_VXE"
@@ -1316,7 +1316,7 @@
(define_insn "neg_fms<mode>4"
[(set (match_operand:VF_HW 0 "register_operand" "=v")
(neg:VF_HW
- (fma:VF_HW (match_operand:VF_HW 1 "register_operand" "%v")
+ (fma:VF_HW (match_operand:VF_HW 1 "register_operand" "v")
(match_operand:VF_HW 2 "register_operand" "v")
(neg:VF_HW (match_operand:VF_HW 3 "register_operand"
"v")))))]
"TARGET_VXE"
@@ -1356,7 +1356,7 @@
; vfmaxsb, vfmaxdb, wfmaxsb, wfmaxdb, wfmaxxb
(define_insn "*smax<mode>3_vxe"
[(set (match_operand:VF_HW 0 "register_operand" "=v")
- (smax:VF_HW (match_operand:VF_HW 1 "register_operand" "%v")
+ (smax:VF_HW (match_operand:VF_HW 1 "register_operand" "v")
(match_operand:VF_HW 2 "register_operand" "v")))]
"TARGET_VXE"
"<vw>fmax<sdx>b\t%v0,%v1,%v2,4"
@@ -1365,7 +1365,7 @@
; Emulate with compare + select
(define_insn_and_split "*smaxv2df3_vx"
[(set (match_operand:V2DF 0 "register_operand" "=v")
- (smax:V2DF (match_operand:V2DF 1 "register_operand" "%v")
+ (smax:V2DF (match_operand:V2DF 1 "register_operand" "v")
(match_operand:V2DF 2 "register_operand" "v")))]
"TARGET_VX && !TARGET_VXE"
"#"
@@ -1392,7 +1392,7 @@
; vfminsb, vfmindb, wfminsb, wfmindb, wfminxb
(define_insn "*smin<mode>3_vxe"
[(set (match_operand:VF_HW 0 "register_operand" "=v")
- (smin:VF_HW (match_operand:VF_HW 1 "register_operand" "%v")
+ (smin:VF_HW (match_operand:VF_HW 1 "register_operand" "v")
(match_operand:VF_HW 2 "register_operand" "v")))]
"TARGET_VXE"
"<vw>fmin<sdx>b\t%v0,%v1,%v2,4"
@@ -1401,7 +1401,7 @@
; Emulate with compare + select
(define_insn_and_split "*sminv2df3_vx"
[(set (match_operand:V2DF 0 "register_operand" "=v")
- (smin:V2DF (match_operand:V2DF 1 "register_operand" "%v")
+ (smin:V2DF (match_operand:V2DF 1 "register_operand" "v")
(match_operand:V2DF 2 "register_operand" "v")))]
"TARGET_VX && !TARGET_VXE"
"#"
diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md
index f13984de954..9a7f3dae1df 100644
--- a/gcc/config/s390/vx-builtins.md
+++ b/gcc/config/s390/vx-builtins.md
@@ -619,7 +619,7 @@
; vaccb, vacch, vaccf, vaccg, vaccq
(define_insn "vacc<bhfgq>_<mode>"
[(set (match_operand:VIT_HW 0 "register_operand" "=v")
- (unspec:VIT_HW [(match_operand:VIT_HW 1 "register_operand" "%v")
+ (unspec:VIT_HW [(match_operand:VIT_HW 1 "register_operand" "v")
(match_operand:VIT_HW 2 "register_operand" "v")]
UNSPEC_VEC_ADDC))]
"TARGET_VX"
@@ -630,7 +630,7 @@
(define_insn "vacq"
[(set (match_operand:TI 0 "register_operand" "=v")
- (unspec:TI [(match_operand:TI 1 "register_operand" "%v")
+ (unspec:TI [(match_operand:TI 1 "register_operand" "v")
(match_operand:TI 2 "register_operand" "v")
(match_operand:TI 3 "register_operand" "v")]
UNSPEC_VEC_ADDE_U128))]
@@ -643,7 +643,7 @@
(define_insn "vacccq"
[(set (match_operand:TI 0 "register_operand" "=v")
- (unspec:TI [(match_operand:TI 1 "register_operand" "%v")
+ (unspec:TI [(match_operand:TI 1 "register_operand" "v")
(match_operand:TI 2 "register_operand" "v")
(match_operand:TI 3 "register_operand" "v")]
UNSPEC_VEC_ADDEC_U128))]
@@ -671,7 +671,7 @@
; vavgb, vavgh, vavgf, vavgg
(define_insn "vec_avg<mode>"
[(set (match_operand:VI_HW 0 "register_operand" "=v")
- (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "%v")
+ (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "v")
(match_operand:VI_HW 2 "register_operand" "v")]
UNSPEC_VEC_AVG))]
"TARGET_VX"
@@ -683,7 +683,7 @@
; vavglb, vavglh, vavglf, vavglg
(define_insn "vec_avgu<mode>"
[(set (match_operand:VI_HW 0 "register_operand" "=v")
- (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "%v")
+ (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "v")
(match_operand:VI_HW 2 "register_operand" "v")]
UNSPEC_VEC_AVGU))]
"TARGET_VX"
@@ -855,9 +855,9 @@
; vmalb, vmalh, vmalf, vmalg
(define_insn "vec_vmal<mode>"
[(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
- (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
- (match_operand:VI_HW_QHS 2 "register_operand" "v")
- (match_operand:VI_HW_QHS 3 "register_operand" "v")]
+ (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
+ (match_operand:VI_HW_QHS 2 "register_operand" "v")
+ (match_operand:VI_HW_QHS 3 "register_operand" "v")]
UNSPEC_VEC_VMAL))]
"TARGET_VX"
"vmal<bhfgq><w>\t%v0,%v1,%v2,%v3"
@@ -868,9 +868,9 @@
; vmahb; vmahh, vmahf, vmahg
(define_insn "vec_vmah<mode>"
[(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
- (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
- (match_operand:VI_HW_QHS 2 "register_operand" "v")
- (match_operand:VI_HW_QHS 3 "register_operand" "v")]
+ (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
+ (match_operand:VI_HW_QHS 2 "register_operand" "v")
+ (match_operand:VI_HW_QHS 3 "register_operand" "v")]
UNSPEC_VEC_VMAH))]
"TARGET_VX"
"vmah<bhfgq>\t%v0,%v1,%v2,%v3"
@@ -878,10 +878,10 @@
; vmalhb; vmalhh, vmalhf, vmalhg
(define_insn "vec_vmalh<mode>"
- [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
- (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
- (match_operand:VI_HW_QHS 2 "register_operand" "v")
- (match_operand:VI_HW_QHS 3 "register_operand" "v")]
+ [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
+ (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
+ (match_operand:VI_HW_QHS 2 "register_operand" "v")
+ (match_operand:VI_HW_QHS 3 "register_operand" "v")]
UNSPEC_VEC_VMALH))]
"TARGET_VX"
"vmalh<bhfgq>\t%v0,%v1,%v2,%v3"
@@ -891,8 +891,8 @@
; vmaeb; vmaeh, vmaef, vmaeg
(define_insn "vec_vmae<mode>"
- [(set (match_operand:<vec_double> 0 "register_operand" "=v")
- (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand"
"%v")
+ [(set (match_operand:<vec_double> 0 "register_operand"
"=v")
+ (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand"
"v")
(match_operand:VI_HW_QHS 2 "register_operand"
"v")
(match_operand:<vec_double> 3 "register_operand"
"v")]
UNSPEC_VEC_VMAE))]
@@ -902,9 +902,9 @@
; vmaleb; vmaleh, vmalef, vmaleg
(define_insn "vec_vmale<mode>"
- [(set (match_operand:<vec_double> 0 "register_operand" "=v")
- (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand"
"%v")
- (match_operand:VI_HW_QHS 2 "register_operand" "v")
+ [(set (match_operand:<vec_double> 0 "register_operand"
"=v")
+ (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand"
"v")
+ (match_operand:VI_HW_QHS 2 "register_operand"
"v")
(match_operand:<vec_double> 3 "register_operand"
"v")]
UNSPEC_VEC_VMALE))]
"TARGET_VX"
@@ -915,9 +915,9 @@
; vmaob; vmaoh, vmaof, vmaog
(define_insn "vec_vmao<mode>"
- [(set (match_operand:<vec_double> 0 "register_operand" "=v")
- (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand"
"%v")
- (match_operand:VI_HW_QHS 2 "register_operand" "v")
+ [(set (match_operand:<vec_double> 0 "register_operand"
"=v")
+ (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand"
"v")
+ (match_operand:VI_HW_QHS 2 "register_operand"
"v")
(match_operand:<vec_double> 3 "register_operand"
"v")]
UNSPEC_VEC_VMAO))]
"TARGET_VX"
@@ -926,9 +926,9 @@
; vmalob; vmaloh, vmalof, vmalog
(define_insn "vec_vmalo<mode>"
- [(set (match_operand:<vec_double> 0 "register_operand" "=v")
- (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand" "v")
- (match_operand:VI_HW_QHS 2 "register_operand" "v")
+ [(set (match_operand:<vec_double> 0 "register_operand"
"=v")
+ (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand"
"v")
+ (match_operand:VI_HW_QHS 2 "register_operand"
"v")
(match_operand:<vec_double> 3 "register_operand"
"v")]
UNSPEC_VEC_VMALO))]
"TARGET_VX"
@@ -942,8 +942,8 @@
; vmhb, vmhh, vmhf
(define_insn "vec_smulh<mode>"
- [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
- (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
+ [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
+ (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
(match_operand:VI_HW_QHS 2 "register_operand" "v")]
UNSPEC_VEC_SMULT_HI))]
"TARGET_VX"
@@ -952,8 +952,8 @@
; vmlhb, vmlhh, vmlhf
(define_insn "vec_umulh<mode>"
- [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
- (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
+ [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
+ (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
(match_operand:VI_HW_QHS 2 "register_operand" "v")]
UNSPEC_VEC_UMULT_HI))]
"TARGET_VX"
@@ -970,9 +970,9 @@
; Vector nor
(define_insn "vec_nor<mode>3"
- [(set (match_operand:VT_HW 0 "register_operand" "=v")
+ [(set (match_operand:VT_HW 0 "register_operand" "=v")
(not:VT_HW
- (ior:VT_HW (match_operand:VT_HW 1 "register_operand" "%v")
+ (ior:VT_HW (match_operand:VT_HW 1 "register_operand" "v")
(match_operand:VT_HW 2 "register_operand" "v"))))]
"TARGET_VX"
"vno\t%v0,%v1,%v2"
@@ -2120,7 +2120,7 @@
[(set (reg:CCVFHE CC_REGNUM)
(compare:CCVFHE (match_operand:VF_HW 0 "register_operand" "v")
(match_operand:VF_HW 1 "register_operand" "v")))
- (set (match_operand:<tointvec> 2 "register_operand" "=v")
+ (set (match_operand:<tointvec> 2 "register_operand" "=v")
(ge:<tointvec> (match_dup 0) (match_dup 1)))]
"TARGET_VX"
"<vw>fche<sdx>bs\t%v2,%v0,%v1"
@@ -2128,9 +2128,9 @@
(define_insn "vfmin<mode>"
- [(set (match_operand:VF_HW 0 "register_operand" "=v")
- (unspec:VF_HW [(match_operand:VF_HW 1 "register_operand" "%v")
- (match_operand:VF_HW 2 "register_operand" "v")
+ [(set (match_operand:VF_HW 0 "register_operand" "=v")
+ (unspec:VF_HW [(match_operand:VF_HW 1 "register_operand" "v")
+ (match_operand:VF_HW 2 "register_operand" "v")
(match_operand:QI 3 "const_mask_operand" "C")]
UNSPEC_VEC_VFMIN))]
"TARGET_VXE"
@@ -2138,9 +2138,9 @@
[(set_attr "op_type" "VRR")])
(define_insn "vfmax<mode>"
- [(set (match_operand:VF_HW 0 "register_operand" "=v")
- (unspec:VF_HW [(match_operand:VF_HW 1 "register_operand" "%v")
- (match_operand:VF_HW 2 "register_operand" "v")
+ [(set (match_operand:VF_HW 0 "register_operand" "=v")
+ (unspec:VF_HW [(match_operand:VF_HW 1 "register_operand" "v")
+ (match_operand:VF_HW 2 "register_operand" "v")
(match_operand:QI 3 "const_mask_operand" "C")]
UNSPEC_VEC_VFMAX))]
"TARGET_VXE"
--
2.17.1
