Now that we're using UNSPEC_ADCS instead of rtl, there's
no reason to distinguish CC_ADCmode from CC_Cmode. Both
examine only the C bit. Within uaddvti4, using CC_Cmode
is clearer, since it's the carry-outthat's relevant.
* config/aarch64/aarch64-modes.def (CC_ADC): Remove.
* config/aarch64/aarch64.c (aarch64_select_cc_mode):
Do not look for unsigned overflow from add with carry.
* config/aarch64/aarch64.md (uaddvti4): Use CC_Cmode.
* config/aarch64/predicates.md (aarch64_carry_operation)
Remove check for CC_ADCmode.
(aarch64_borrow_operation): Likewise.
---
gcc/config/aarch64/aarch64.c | 19 -------------------
gcc/config/aarch64/aarch64-modes.def | 1 -
gcc/config/aarch64/aarch64.md | 2 +-
gcc/config/aarch64/predicates.md | 4 ++--
4 files changed, 3 insertions(+), 23 deletions(-)
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 6263897c9a0..8e54506bc3e 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -9094,16 +9094,6 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
&& rtx_equal_p (XEXP (x, 0), y))
return CC_Cmode;
- /* A test for unsigned overflow from an add with carry. */
- if ((mode_x == DImode || mode_x == TImode)
- && (code == LTU || code == GEU)
- && code_x == PLUS
- && CONST_SCALAR_INT_P (y)
- && (rtx_mode_t (y, mode_x)
- == (wi::shwi (1, mode_x)
- << (GET_MODE_BITSIZE (mode_x).to_constant () / 2))))
- return CC_ADCmode;
-
/* A test for signed overflow. */
if ((mode_x == DImode || mode_x == TImode)
&& code == NE
@@ -9232,15 +9222,6 @@ aarch64_get_condition_code_1 (machine_mode mode, enum
rtx_code comp_code)
}
break;
- case E_CC_ADCmode:
- switch (comp_code)
- {
- case GEU: return AARCH64_CS;
- case LTU: return AARCH64_CC;
- default: return -1;
- }
- break;
-
case E_CC_Vmode:
switch (comp_code)
{
diff --git a/gcc/config/aarch64/aarch64-modes.def
b/gcc/config/aarch64/aarch64-modes.def
index af972e8f72b..32e4b6a35a9 100644
--- a/gcc/config/aarch64/aarch64-modes.def
+++ b/gcc/config/aarch64/aarch64-modes.def
@@ -38,7 +38,6 @@ CC_MODE (CC_NZC); /* Only N, Z and C bits of condition
flags are valid.
CC_MODE (CC_NZ); /* Only N and Z bits of condition flags are valid. */
CC_MODE (CC_Z); /* Only Z bit of condition flags is valid. */
CC_MODE (CC_C); /* C represents unsigned overflow of a simple addition. */
-CC_MODE (CC_ADC); /* Unsigned overflow from an ADC (add with carry). */
CC_MODE (CC_V); /* Only V bit of condition flags is valid. */
/* Half-precision floating point for __fp16. */
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 99023494fa1..8d405b40173 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -2079,7 +2079,7 @@
CODE_FOR_adddi3_compareC,
CODE_FOR_adddi3_compareC,
CODE_FOR_adddi3_carryin_cmp);
- aarch64_gen_unlikely_cbranch (GEU, CC_ADCmode, operands[3]);
+ aarch64_gen_unlikely_cbranch (LTU, CC_Cmode, operands[3]);
DONE;
})
diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md
index 5f44ef7d672..42864cbf4dd 100644
--- a/gcc/config/aarch64/predicates.md
+++ b/gcc/config/aarch64/predicates.md
@@ -388,7 +388,7 @@
machine_mode ccmode = GET_MODE (op0);
if (ccmode == CC_Cmode)
return GET_CODE (op) == LTU;
- if (ccmode == CC_ADCmode || ccmode == CCmode)
+ if (ccmode == CCmode)
return GET_CODE (op) == GEU;
return false;
})
@@ -406,7 +406,7 @@
machine_mode ccmode = GET_MODE (op0);
if (ccmode == CC_Cmode)
return GET_CODE (op) == GEU;
- if (ccmode == CC_ADCmode || ccmode == CCmode)
+ if (ccmode == CCmode)
return GET_CODE (op) == LTU;
return false;
})
--
2.20.1
