From 20489d30b7227ea62f9fb618bd5affb637567363 Mon Sep 17 00:00:00 2001 From: Joe Ramsay Date: Thu, 28 May 2020 14:28:31 +0000 Subject: [PATCH] Support AND, ORR, EOR on unpacked vectors Extended patterns for these instructions. BIC will have to wait, as there is not currently support for unpacked NOT 2020-05-20 Joe Ramsay * config/aarch64/aarch64-sve.md (3): Add support for unpacked EOR, ORR, AND. gcc/testsuite/ChangeLog 2020-05-20 Joe Ramsay * gcc.target/aarch64/sve/load_const_offset_2.c: Force using packed vectors. * gcc.target/aarch64/sve/logical_unpacked_and_1.c: New test. * gcc.target/aarch64/sve/logical_unpacked_and_2.c: New test. * gcc.target/aarch64/sve/logical_unpacked_and_3.c: New test. * gcc.target/aarch64/sve/logical_unpacked_and_4.c: New test. * gcc.target/aarch64/sve/logical_unpacked_and_5.c: New test. * gcc.target/aarch64/sve/logical_unpacked_and_6.c: New test. * gcc.target/aarch64/sve/logical_unpacked_and_7.c: New test. * gcc.target/aarch64/sve/logical_unpacked_eor_1.c: New test. * gcc.target/aarch64/sve/logical_unpacked_eor_2.c: New test. * gcc.target/aarch64/sve/logical_unpacked_eor_3.c: New test. * gcc.target/aarch64/sve/logical_unpacked_eor_4.c: New test. * gcc.target/aarch64/sve/logical_unpacked_eor_5.c: New test. * gcc.target/aarch64/sve/logical_unpacked_eor_6.c: New test. * gcc.target/aarch64/sve/logical_unpacked_eor_7.c: New test. * gcc.target/aarch64/sve/logical_unpacked_orr_1.c: New test. * gcc.target/aarch64/sve/logical_unpacked_orr_2.c: New test. * gcc.target/aarch64/sve/logical_unpacked_orr_3.c: New test. * gcc.target/aarch64/sve/logical_unpacked_orr_4.c: New test. * gcc.target/aarch64/sve/logical_unpacked_orr_5.c: New test. * gcc.target/aarch64/sve/logical_unpacked_orr_6.c: New test. * gcc.target/aarch64/sve/logical_unpacked_orr_7.c: New test. * gcc.target/aarch64/sve/scatter_store_6.c: Force using packed vectors. * gcc.target/aarch64/sve/scatter_store_7.c: Force using packed vectors. * gcc.target/aarch64/sve/strided_load_3.c: Force using packed vectors. * gcc.target/aarch64/sve/strided_store_3.c: Force using packed vectors. * gcc.target/aarch64/sve/unpack_signed_1.c: Force using packed vectors. --- gcc/config/aarch64/aarch64-sve.md | 8 ++++---- .../gcc.target/aarch64/sve/load_const_offset_2.c | 2 +- .../gcc.target/aarch64/sve/logical_unpacked_and_1.c | 16 ++++++++++++++++ .../gcc.target/aarch64/sve/logical_unpacked_and_2.c | 17 +++++++++++++++++ .../gcc.target/aarch64/sve/logical_unpacked_and_3.c | 17 +++++++++++++++++ .../gcc.target/aarch64/sve/logical_unpacked_and_4.c | 17 +++++++++++++++++ .../gcc.target/aarch64/sve/logical_unpacked_and_5.c | 16 ++++++++++++++++ .../gcc.target/aarch64/sve/logical_unpacked_and_6.c | 17 +++++++++++++++++ .../gcc.target/aarch64/sve/logical_unpacked_and_7.c | 16 ++++++++++++++++ .../gcc.target/aarch64/sve/logical_unpacked_eor_1.c | 16 ++++++++++++++++ .../gcc.target/aarch64/sve/logical_unpacked_eor_2.c | 17 +++++++++++++++++ .../gcc.target/aarch64/sve/logical_unpacked_eor_3.c | 17 +++++++++++++++++ .../gcc.target/aarch64/sve/logical_unpacked_eor_4.c | 17 +++++++++++++++++ .../gcc.target/aarch64/sve/logical_unpacked_eor_5.c | 16 ++++++++++++++++ .../gcc.target/aarch64/sve/logical_unpacked_eor_6.c | 17 +++++++++++++++++ .../gcc.target/aarch64/sve/logical_unpacked_eor_7.c | 16 ++++++++++++++++ .../gcc.target/aarch64/sve/logical_unpacked_orr_1.c | 16 ++++++++++++++++ .../gcc.target/aarch64/sve/logical_unpacked_orr_2.c | 17 +++++++++++++++++ .../gcc.target/aarch64/sve/logical_unpacked_orr_3.c | 17 +++++++++++++++++ .../gcc.target/aarch64/sve/logical_unpacked_orr_4.c | 17 +++++++++++++++++ .../gcc.target/aarch64/sve/logical_unpacked_orr_5.c | 16 ++++++++++++++++ .../gcc.target/aarch64/sve/logical_unpacked_orr_6.c | 17 +++++++++++++++++ .../gcc.target/aarch64/sve/logical_unpacked_orr_7.c | 16 ++++++++++++++++ gcc/testsuite/gcc.target/aarch64/sve/scatter_store_6.c | 2 +- gcc/testsuite/gcc.target/aarch64/sve/scatter_store_7.c | 2 +- gcc/testsuite/gcc.target/aarch64/sve/strided_load_3.c | 2 +- gcc/testsuite/gcc.target/aarch64/sve/strided_store_3.c | 2 +- gcc/testsuite/gcc.target/aarch64/sve/unpack_signed_1.c | 2 +- 28 files changed, 358 insertions(+), 10 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_5.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_6.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_7.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_5.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_6.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_7.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_5.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_6.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_7.c diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index f7a0893..8f0944c 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -4211,10 +4211,10 @@ ;; Unpredicated integer binary logical operations. (define_insn "3" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?w, w") - (LOGICAL:SVE_FULL_I - (match_operand:SVE_FULL_I 1 "register_operand" "%0, w, w") - (match_operand:SVE_FULL_I 2 "aarch64_sve_logical_operand" "vsl, vsl, w")))] + [(set (match_operand:SVE_I 0 "register_operand" "=w, ?w, w") + (LOGICAL:SVE_I + (match_operand:SVE_I 1 "register_operand" "%0, w, w") + (match_operand:SVE_I 2 "aarch64_sve_logical_operand" "vsl, vsl, w")))] "TARGET_SVE" "@ \t%0., %0., #%C2 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/load_const_offset_2.c b/gcc/testsuite/gcc.target/aarch64/sve/load_const_offset_2.c index e02a6b5..0aab81b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/load_const_offset_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/load_const_offset_2.c @@ -1,5 +1,5 @@ /* { dg-do assemble { target aarch64_asm_sve_ok } } */ -/* { dg-options "-O2 -ftree-vectorize -save-temps" } */ +/* { dg-options "-O2 -ftree-vectorize -save-temps --param aarch64-sve-compare-costs=0" } */ #include diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_1.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_1.c new file mode 100644 index 0000000..7840355 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_1.c @@ -0,0 +1,16 @@ +/* { dg-options "-O3 -msve-vector-bits=256" } */ + +#include + +void +f (uint32_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2) +{ + for (int i = 0; i < 7; ++i) + dst[i] = (uint16_t) (src1[i] & src2[i]); +} + +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s,} 1 } } */ +/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.s,} 1 } } */ +/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.s,} 1 } } */ +/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s,} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_2.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_2.c new file mode 100644 index 0000000..08b2745 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_2.c @@ -0,0 +1,17 @@ +/* { dg-options "-O3 -msve-vector-bits=256" } */ + +#include + +void +f (uint64_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2) +{ + for (int i = 0; i < 7; ++i) + dst[i] = (uint16_t) (src1[i] & src2[i]); +} + +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.h,} 1 } } */ +/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_3.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_3.c new file mode 100644 index 0000000..c823470 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_3.c @@ -0,0 +1,17 @@ +/* { dg-options "-O3 -msve-vector-bits=256" } */ + +#include + +void +f (uint64_t *restrict dst, uint32_t *restrict src1, uint8_t *restrict src2) +{ + for (int i = 0; i < 7; ++i) + dst[i] = (uint32_t) (src1[i] & src2[i]); +} + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.s,} 1 } } */ +/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_4.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_4.c new file mode 100644 index 0000000..52c9291 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_4.c @@ -0,0 +1,17 @@ +/* { dg-options "-O3 -msve-vector-bits=256" } */ + +#include + +void +f (uint64_t *restrict dst, uint32_t *restrict src1, uint16_t *restrict src2) +{ + for (int i = 0; i < 7; ++i) + dst[i] = (uint32_t) (src1[i] & src2[i]); +} + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.s,} 1 } } */ +/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_5.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_5.c new file mode 100644 index 0000000..7840355 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_5.c @@ -0,0 +1,16 @@ +/* { dg-options "-O3 -msve-vector-bits=256" } */ + +#include + +void +f (uint32_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2) +{ + for (int i = 0; i < 7; ++i) + dst[i] = (uint16_t) (src1[i] & src2[i]); +} + +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s,} 1 } } */ +/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.s,} 1 } } */ +/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.s,} 1 } } */ +/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s,} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_6.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_6.c new file mode 100644 index 0000000..1552ed8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_6.c @@ -0,0 +1,17 @@ +/* { dg-options "-O3 -msve-vector-bits=256" } */ + +#include + +void +f (uint64_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2) +{ + for (int i = 0; i < 7; ++i) + dst[i] = (uint16_t) (src1[i] & src2[i]); +} + +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.h,} 1 } } */ +/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_7.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_7.c new file mode 100644 index 0000000..484d9da --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_7.c @@ -0,0 +1,16 @@ +/* { dg-options "-O3 -msve-vector-bits=256" } */ + +#include + +void +f (uint64_t *restrict dst, uint32_t *restrict src1, uint8_t *restrict src2){ + for (int i = 0; i < 7; ++i) + dst[i] = (uint32_t) (src1[i] & src2[i]); +} + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.s,} 1 } } */ +/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_1.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_1.c new file mode 100644 index 0000000..36a0b8c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_1.c @@ -0,0 +1,16 @@ +/* { dg-options "-O3 -msve-vector-bits=256" } */ + +#include + +void +f (uint32_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2) +{ + for (int i = 0; i < 7; ++i) + dst[i] = (uint16_t) (src1[i] ^ src2[i]); +} + +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s,} 1 } } */ +/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.s,} 1 } } */ +/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.s,} 1 } } */ +/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s,} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_2.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_2.c new file mode 100644 index 0000000..23ddeb9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_2.c @@ -0,0 +1,17 @@ +/* { dg-options "-O3 -msve-vector-bits=256" } */ + +#include + +void +f (uint64_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2) +{ + for (int i = 0; i < 7; ++i) + dst[i] = (uint16_t) (src1[i] ^ src2[i]); +} + +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.h,} 1 } } */ +/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_3.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_3.c new file mode 100644 index 0000000..4dd1e08 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_3.c @@ -0,0 +1,17 @@ +/* { dg-options "-O3 -msve-vector-bits=256" } */ + +#include + +void +f (uint64_t *restrict dst, uint32_t *restrict src1, uint8_t *restrict src2) +{ + for (int i = 0; i < 7; ++i) + dst[i] = (uint32_t) (src1[i] ^ src2[i]); +} + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.s,} 1 } } */ +/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_4.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_4.c new file mode 100644 index 0000000..a31a2d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_4.c @@ -0,0 +1,17 @@ +/* { dg-options "-O3 -msve-vector-bits=256" } */ + +#include + +void +f (uint64_t *restrict dst, uint32_t *restrict src1, uint16_t *restrict src2) +{ + for (int i = 0; i < 7; ++i) + dst[i] = (uint32_t) (src1[i] ^ src2[i]); +} + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.s,} 1 } } */ +/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_5.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_5.c new file mode 100644 index 0000000..36a0b8c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_5.c @@ -0,0 +1,16 @@ +/* { dg-options "-O3 -msve-vector-bits=256" } */ + +#include + +void +f (uint32_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2) +{ + for (int i = 0; i < 7; ++i) + dst[i] = (uint16_t) (src1[i] ^ src2[i]); +} + +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s,} 1 } } */ +/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.s,} 1 } } */ +/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.s,} 1 } } */ +/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s,} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_6.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_6.c new file mode 100644 index 0000000..416567b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_6.c @@ -0,0 +1,17 @@ +/* { dg-options "-O3 -msve-vector-bits=256" } */ + +#include + +void +f (uint64_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2) +{ + for (int i = 0; i < 7; ++i) + dst[i] = (uint16_t) (src1[i] ^ src2[i]); +} + +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.h,} 1 } } */ +/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_7.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_7.c new file mode 100644 index 0000000..3f7c3dd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_7.c @@ -0,0 +1,16 @@ +/* { dg-options "-O3 -msve-vector-bits=256" } */ + +#include + +void +f (uint64_t *restrict dst, uint32_t *restrict src1, uint8_t *restrict src2){ + for (int i = 0; i < 7; ++i) + dst[i] = (uint32_t) (src1[i] ^ src2[i]); +} + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.s,} 1 } } */ +/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_1.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_1.c new file mode 100644 index 0000000..6131792 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_1.c @@ -0,0 +1,16 @@ +/* { dg-options "-O3 -msve-vector-bits=256" } */ + +#include + +void +f (uint32_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2) +{ + for (int i = 0; i < 7; ++i) + dst[i] = (uint16_t) (src1[i] | src2[i]); +} + +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s,} 1 } } */ +/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.s,} 1 } } */ +/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.s,} 1 } } */ +/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s,} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_2.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_2.c new file mode 100644 index 0000000..593de65 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_2.c @@ -0,0 +1,17 @@ +/* { dg-options "-O3 -msve-vector-bits=256" } */ + +#include + +void +f (uint64_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2) +{ + for (int i = 0; i < 7; ++i) + dst[i] = (uint16_t) (src1[i] | src2[i]); +} + +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.h,} 1 } } */ +/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_3.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_3.c new file mode 100644 index 0000000..ec34e75 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_3.c @@ -0,0 +1,17 @@ +/* { dg-options "-O3 -msve-vector-bits=256" } */ + +#include + +void +f (uint64_t *restrict dst, uint32_t *restrict src1, uint8_t *restrict src2) +{ + for (int i = 0; i < 7; ++i) + dst[i] = (uint32_t) (src1[i] | src2[i]); +} + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.s,} 1 } } */ +/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_4.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_4.c new file mode 100644 index 0000000..561a104 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_4.c @@ -0,0 +1,17 @@ +/* { dg-options "-O3 -msve-vector-bits=256" } */ + +#include + +void +f (uint64_t *restrict dst, uint32_t *restrict src1, uint16_t *restrict src2) +{ + for (int i = 0; i < 7; ++i) + dst[i] = (uint32_t) (src1[i] | src2[i]); +} + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.s,} 1 } } */ +/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_5.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_5.c new file mode 100644 index 0000000..6131792 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_5.c @@ -0,0 +1,16 @@ +/* { dg-options "-O3 -msve-vector-bits=256" } */ + +#include + +void +f (uint32_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2) +{ + for (int i = 0; i < 7; ++i) + dst[i] = (uint16_t) (src1[i] | src2[i]); +} + +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s,} 1 } } */ +/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.s,} 1 } } */ +/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.s,} 1 } } */ +/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s,} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_6.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_6.c new file mode 100644 index 0000000..3ce1c3f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_6.c @@ -0,0 +1,17 @@ +/* { dg-options "-O3 -msve-vector-bits=256" } */ + +#include + +void +f (uint64_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2) +{ + for (int i = 0; i < 7; ++i) + dst[i] = (uint16_t) (src1[i] | src2[i]); +} + +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.h,} 1 } } */ +/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_7.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_7.c new file mode 100644 index 0000000..e6a4291 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_7.c @@ -0,0 +1,16 @@ +/* { dg-options "-O3 -msve-vector-bits=256" } */ + +#include + +void +f (uint64_t *restrict dst, uint32_t *restrict src1, uint8_t *restrict src2){ + for (int i = 0; i < 7; ++i) + dst[i] = (uint32_t) (src1[i] | src2[i]); +} + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.s,} 1 } } */ +/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */ +/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/scatter_store_6.c b/gcc/testsuite/gcc.target/aarch64/sve/scatter_store_6.c index ee31562..a9c37c4 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/scatter_store_6.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/scatter_store_6.c @@ -1,5 +1,5 @@ /* { dg-do assemble { target aarch64_asm_sve_ok } } */ -/* { dg-options "-O2 -ftree-vectorize -fwrapv --save-temps" } */ +/* { dg-options "-O2 -ftree-vectorize -fwrapv --save-temps --param aarch64-sve-compare-costs=0" } */ #include diff --git a/gcc/testsuite/gcc.target/aarch64/sve/scatter_store_7.c b/gcc/testsuite/gcc.target/aarch64/sve/scatter_store_7.c index 784921e..147eadc 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/scatter_store_7.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/scatter_store_7.c @@ -1,5 +1,5 @@ /* { dg-do assemble { target aarch64_asm_sve_ok } } */ -/* { dg-options "-O2 -ftree-vectorize --save-temps" } */ +/* { dg-options "-O2 -ftree-vectorize --save-temps --param aarch64-sve-compare-costs=0" } */ #define INDEX16 uint16_t #define INDEX32 uint32_t diff --git a/gcc/testsuite/gcc.target/aarch64/sve/strided_load_3.c b/gcc/testsuite/gcc.target/aarch64/sve/strided_load_3.c index 8f720dc..2e7cd98 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/strided_load_3.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/strided_load_3.c @@ -1,5 +1,5 @@ /* { dg-do assemble { target aarch64_asm_sve_ok } } */ -/* { dg-options "-O2 -ftree-vectorize --save-temps" } */ +/* { dg-options "-O2 -ftree-vectorize --save-temps --param aarch64-sve-compare-costs=0" } */ #include diff --git a/gcc/testsuite/gcc.target/aarch64/sve/strided_store_3.c b/gcc/testsuite/gcc.target/aarch64/sve/strided_store_3.c index 68835af..335f99b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/strided_store_3.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/strided_store_3.c @@ -1,5 +1,5 @@ /* { dg-do assemble { target aarch64_asm_sve_ok } } */ -/* { dg-options "-O2 -ftree-vectorize --save-temps" } */ +/* { dg-options "-O2 -ftree-vectorize --save-temps --param aarch64-sve-compare-costs=0" } */ #include diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpack_signed_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpack_signed_1.c index d4da369..ecb6e99 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/unpack_signed_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpack_signed_1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -ftree-vectorize -fno-inline" } */ +/* { dg-options "-O2 -ftree-vectorize -fno-inline --param aarch64-sve-compare-costs=0" } */ #include -- 2.7.4