From e7621794f048869dc12212dd99e62c0b681aa8f1 Mon Sep 17 00:00:00 2001 From: liuhongt Date: Fri, 29 May 2020 13:38:49 +0800 Subject: [PATCH] Fix zero-masking for vcvtps2ph when dest operand is memory. When dest is memory, zero-masking is not valid, only merging-masking is available, gcc/ChangeLog: * gcc/config/i386/sse.md (*vcvtps2ph_store): Refine from *vcvtps2ph_store. (vcvtps2ph256): Refine constraint from vm to v. (avx512f_vcvtps2ph512): Ditto. (*vcvtps2ph256): New define_insn. (*avx512f_vcvtps2ph512): Ditto. * gcc/config/i386/subst.md (merge_mask): New define_subst. (merge_mask_name): New define_subst_attr. (merge_mask_operand3): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/avx512f-vcvtps2ph-pr95254.c: New test. * gcc.target/i386/avx512vl-vcvtps2ph-pr95254.c: Ditto. --- gcc/config/i386/sse.md | 32 ++++++++++++++++--- gcc/config/i386/subst.md | 12 +++++++ .../i386/avx512f-vcvtps2ph-pr95254.c | 12 +++++++ .../i386/avx512vl-vcvtps2ph-pr95254.c | 18 +++++++++++ 4 files changed, 70 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-vcvtps2ph-pr95254.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-vcvtps2ph-pr95254.c diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index f2a5a34284d..cce08d3e5ec 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -21773,19 +21773,19 @@ (set_attr "prefix" "maybe_evex") (set_attr "mode" "V4SF")]) -(define_insn "*vcvtps2ph_store" +(define_insn "*vcvtps2ph_store" [(set (match_operand:V4HI 0 "memory_operand" "=m") (unspec:V4HI [(match_operand:V4SF 1 "register_operand" "v") (match_operand:SI 2 "const_0_to_255_operand" "N")] UNSPEC_VCVTPS2PH))] "TARGET_F16C || TARGET_AVX512VL" - "vcvtps2ph\t{%2, %1, %0|%0, %1, %2}" + "vcvtps2ph\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "ssecvt") (set_attr "prefix" "maybe_evex") (set_attr "mode" "V4SF")]) (define_insn "vcvtps2ph256" - [(set (match_operand:V8HI 0 "nonimmediate_operand" "=vm") + [(set (match_operand:V8HI 0 "register_operand" "=v") (unspec:V8HI [(match_operand:V8SF 1 "register_operand" "v") (match_operand:SI 2 "const_0_to_255_operand" "N")] UNSPEC_VCVTPS2PH))] @@ -21796,8 +21796,20 @@ (set_attr "btver2_decode" "vector") (set_attr "mode" "V8SF")]) +(define_insn "*vcvtps2ph256" + [(set (match_operand:V8HI 0 "memory_operand" "=m") + (unspec:V8HI [(match_operand:V8SF 1 "register_operand" "v") + (match_operand:SI 2 "const_0_to_255_operand" "N")] + UNSPEC_VCVTPS2PH))] + "TARGET_F16C || TARGET_AVX512VL" + "vcvtps2ph\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "type" "ssecvt") + (set_attr "prefix" "maybe_evex") + (set_attr "btver2_decode" "vector") + (set_attr "mode" "V8SF")]) + (define_insn "avx512f_vcvtps2ph512" - [(set (match_operand:V16HI 0 "nonimmediate_operand" "=vm") + [(set (match_operand:V16HI 0 "register_operand" "=v") (unspec:V16HI [(match_operand:V16SF 1 "register_operand" "v") (match_operand:SI 2 "const_0_to_255_operand" "N")] @@ -21808,6 +21820,18 @@ (set_attr "prefix" "evex") (set_attr "mode" "V16SF")]) +(define_insn "*avx512f_vcvtps2ph512" + [(set (match_operand:V16HI 0 "memory_operand" "=m") + (unspec:V16HI + [(match_operand:V16SF 1 "register_operand" "v") + (match_operand:SI 2 "const_0_to_255_operand" "N")] + UNSPEC_VCVTPS2PH))] + "TARGET_AVX512F" + "vcvtps2ph\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "type" "ssecvt") + (set_attr "prefix" "evex") + (set_attr "mode" "V16SF")]) + ;; For gather* insn patterns (define_mode_iterator VEC_GATHER_MODE [V2DI V2DF V4DI V4DF V4SI V4SF V8SI V8SF]) diff --git a/gcc/config/i386/subst.md b/gcc/config/i386/subst.md index a5ca144c7f7..58ea9dc83e2 100644 --- a/gcc/config/i386/subst.md +++ b/gcc/config/i386/subst.md @@ -73,6 +73,18 @@ (match_operand:SUBST_V 2 "nonimm_or_0_operand" "0C") (match_operand: 3 "register_operand" "Yk")))]) +(define_subst_attr "merge_mask_name" "merge_mask" "" "_merge_mask") +(define_subst_attr "merge_mask_operand3" "merge_mask" "" "%{%3%}") +(define_subst "merge_mask" + [(set (match_operand:SUBST_V 0) + (match_operand:SUBST_V 1))] + "TARGET_AVX512F" + [(set (match_dup 0) + (vec_merge:SUBST_V + (match_dup 1) + (match_dup 0) + (match_operand: 2 "register_operand" "Yk")))]) + (define_subst_attr "mask_scalar_merge_name" "mask_scalar_merge" "" "_mask") (define_subst_attr "mask_scalar_merge_operand3" "mask_scalar_merge" "" "%{%3%}") (define_subst_attr "mask_scalar_merge_operand4" "mask_scalar_merge" "" "%{%4%}") diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2ph-pr95254.c b/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2ph-pr95254.c new file mode 100644 index 00000000000..9e0da947368 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2ph-pr95254.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512f" } */ + +#include +extern __m256i res; +void +foo (__m512 a, __mmask16 m) +{ + res = _mm512_maskz_cvtps_ph (m, a, 10); +} + +/* { dg-final { scan-assembler-not "vcvtps2ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]\[^\n\]*res\[^\n\]*\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)"} } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vcvtps2ph-pr95254.c b/gcc/testsuite/gcc.target/i386/avx512vl-vcvtps2ph-pr95254.c new file mode 100644 index 00000000000..0c685ea66fd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vcvtps2ph-pr95254.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512vl -mavx512f" } */ + +#include +extern __m128i res; +void +foo (__m256 a, __mmask8 m) +{ + res = _mm256_maskz_cvtps_ph (m, a, 10); +} + +void +foo1 (__m128 a, __mmask8 m) +{ + res = _mm_maskz_cvtps_ph (m, a, 10); +} + +/* { dg-final { scan-assembler-not "vcvtps2ph\[ \\t\]+\[^\{\n\]*%\[xy\]mm\[0-9\]\[^\n\]*res\[^\n\]*\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)"} } */ -- 2.18.1