On Fri, Jun 12, 2020 at 7:30 AM 戎杰杰(无音) <jiejie....@alibaba-inc.com> wrote:
> - The first version for vector extension and verified on rv64imafdcv linux 
> target with qemu.

There is no RISC-V vector extension.  There is only a draft proposal
to add one to the ISA.  Our policy has always been to wait for draft
proposals to be accepted into the ISA before we support them in the
mainline sources.  This is because if we make a release supporting a
draft, and the draft is incompatible with the final proposal, then we
will be stuck supporting two incompatible versions of the same feature
for a long time.

These patches are implementing an obsolete version of the vector
proposal, one which. is already seriously incompatible with current
drafts.  This is a v0.7.1 implementation, which is not compatible with
the current v0.9 draft.  Plans are to try to have a final proposal by
the end of year.

There is also the problem that this is not a fully general
implementation of the vector spec, but one that can only work on
Alibaba parts.  A correct fully general implementation should look
more like the arm sve port using sizeless types and polynomial
register sizes.

I would suggest creating a vendor branch, and adding your patches to
your vendor branch.


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