On Wed, May 27, 2020 at 08:50:43AM -0700, Carl Love wrote:
> The following patch adds support for builtins vec_genbm(), vec_genhm(),
> vec_genwm(), vec_gendm(), vec_genqm(), vec_cntm(), vec_expandm(),
> vec_extractm(). Support for instructions mtvsrbm, mtvsrhm, mtvsrwm,
> mtvsrdm, mtvsrqm, cntm, vexpandm, vextractm.
> +;; Mode attribute to give the suffix for the mask instruction
> +(define_mode_attr VSX_MM_SUFFIX [(V16QI "b") (V8HI "h") (V4SI "w") (V2DI
> "d") (V1TI "q")])
Please shorten that line? It doesn't have to be one line ;-)
> +(define_expand "vec_mtvsrbm_mtvsrbmi"
> +
> + [(set (match_operand:V16QI 0 "vsx_register_operand" "=v")
> + (unspec:V16QI [(match_operand:DI 1 "gpc_reg_operand" "b")]
> + UNSPEC_MTVSBM))]
> + "TARGET_FUTURE"
> + {
> + /* Six bit constant operand. */
> + if (IN_RANGE (INTVAL (operands[1]), 0, 63))
> + emit_insn (gen_vec_mtvsrbmi (operands[0], operands[1]));
> + else
> + emit_insn (gen_vec_mtvsr_v16qi (operands[0], operands[1]));
operands[1] isn't a CONST_INT (it is a REG), so this won't work (INTVAL
on it will ICE with checking, and do something non-sensical otherwise).
So needs a test first? Could just use u6bit_cint_operand even, and lose
the explicit IN_RANGE.
> +(define_insn "vec_mtvsr_<mode>"
> + [(set (match_operand:VSX_MM 0 "vsx_register_operand" "=v")
> + (unspec:VSX_MM [(match_operand:DI 1 "gpc_reg_operand" "b")]
> + UNSPEC_MTVSBM))]
> + "TARGET_FUTURE"
> + "mtvsr<VSX_MM_SUFFIX>m %0,%1";
> + [(set_attr "type" "vecsimple")])
vsx_register_operand together with a "v" constraint is curious, btw.
It is used in a few more places, and it probably works, but would
altivec_register_operand be better?
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c
> @@ -0,0 +1,149 @@
> +/* { dg-do run } */
> +/* { dg-options "-mcpu=future -O2 -save-temps" } */
> +/* { dg-require-effective-target powerpc_future_hw } */
Drop the -save-temps? (Same in the other tests.)
Looks good otherwise.
Segher
