diff --git a/gcc/ira.c b/gcc/ira.c
index a655ae1..f3e50d3 100644
--- a/gcc/ira.c
+++ b/gcc/ira.c
@@ -5126,8 +5126,10 @@ move_unallocated_pseudos (void)
 		   INSN_UID (newinsn), i);
 	SET_REG_N_REFS (i, 0);
       }
+
+  first_moveable_pseudo = last_moveable_pseudo = 0;
 }
-
+
 /* If the backend knows where to allocate pseudos for hard
    register initial values, register these allocations now.  */
 static void
diff --git a/gcc/testsuite/gcc.target/aarch64/nospill.c b/gcc/testsuite/gcc.target/aarch64/nospill.c
new file mode 100644
index 0000000..968a426
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/nospill.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+/* The pseudo for P is marked as moveable in the IRA pass. */
+float
+func_0 (float a, float b, float c)
+{
+  float p = c / a;
+
+  if (b > 1)
+    {
+      b /= p;
+      if (c > 2)
+        a /= 3;
+    }
+
+  return b / c * a;
+}
+
+/* If first_moveable_pseudo and last_moveable_pseudo are not reset correctly,
+   they will carry over and spill the pseudo for Q. */
+float
+func_1 (float a, float b, float c)
+{
+  float q = a + b;
+
+  c *= a / (b + b);
+  if (a > 0)
+    c *= q;
+
+  return a * b * c;
+}
+
+/* We have plenty of spare registers, so check nothing has been spilled. */
+/* { dg-final { scan-assembler-not "\tstr\t" } } */