I'm having trouble understanding why different ports chose their
various constants--e.g., SPARC uses 1<<29 for 32-bit and 1<<43 for
64-bit, whereas x86 uses 1<<29 and 0x7fff8000, respectively. So I
can't comment on the choice of the constant 1<<36 for RISC-V. But
isn't it a problem that 1<<36 is not a valid Pmode value for ILP32?
On Wed, Aug 19, 2020 at 1:02 AM Joshua via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> From: cooper.joshua <cooper.jos...@linux.alibaba.com>
>
> gcc/
>
> * config/riscv/riscv.c (asan_shadow_offset): Implement the offset of
> asan shadow memory for risc-v.
> (asan_shadow_offset): new macro definition.
> ---
>
> gcc/config/riscv/riscv.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
> index 63b0c38..b85b459 100644
> --- a/gcc/config/riscv/riscv.c
> +++ b/gcc/config/riscv/riscv.c
> @@ -5292,6 +5292,14 @@ riscv_gpr_save_operation_p (rtx op)
> return true;
> }
>
> +/* Implement TARGET_ASAN_SHADOW_OFFSET. */
> +
> +static unsigned HOST_WIDE_INT
> +riscv_asan_shadow_offset (void)
> +{
> + return HOST_WIDE_INT_1U << 36;
> +}
> +
> /* Initialize the GCC target structure. */
> #undef TARGET_ASM_ALIGNED_HI_OP
> #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
> @@ -5475,6 +5483,9 @@ riscv_gpr_save_operation_p (rtx op)
> #undef TARGET_NEW_ADDRESS_PROFITABLE_P
> #define TARGET_NEW_ADDRESS_PROFITABLE_P riscv_new_address_profitable_p
>
> +#undef TARGET_ASAN_SHADOW_OFFSET
> +#define TARGET_ASAN_SHADOW_OFFSET riscv_asan_shadow_offset
> +
> struct gcc_target targetm = TARGET_INITIALIZER;
>
> #include "gt-riscv.h"
> --
> 2.7.4
>
