Hello,
Following on from the earlier patch to fix up the syntax for
add/sub/adds/subs and friends with a sign/zero-extended operand [0],
this patch removes the "mult" variants of these patterns which are
all redundant.
This patch removes the following patterns from the AArch64 backend:
*adds_mul_imm_<mode>
*subs_mul_imm_<mode>
*adds_<optab><mode>_multp2
*subs_<optab><mode>_multp2
*add_mul_imm_<mode>
*add_<optab><ALLX:mode>_mult_<GPI:mode>
*add_<optab><SHORT:mode>_mult_si_uxtw
*add_<optab><mode>_multp2
*add_<optab>si_multp2_uxtw
*add_uxt<mode>_multp2
*add_uxtsi_multp2_uxtw
*sub_mul_imm_<mode>
*sub_mul_imm_si_uxtw
*sub_<optab><mode>_multp2
*sub_<optab>si_multp2_uxtw
*sub_uxt<mode>_multp2
*sub_uxtsi_multp2_uxtw
*neg_mul_imm_<mode>2
*neg_mul_imm_si2_uxtw
Together with the following predicates which were used only by these
patterns:
- aarch64_pwr_imm3
- aarch64_pwr_2_si
- aarch64_pwr_2_di
These patterns are all redundant since multiplications by powers of two
should be represented as shfits outside a (mem).
Testing:
* Bootstrapped and regtested on aarch64-none-linux-gnu (on top of [0]),
no regressions.
OK for master (when applied after [0])?
Thanks,
Alex
[0] : https://gcc.gnu.org/pipermail/gcc-patches/2020-August/552137.html
---
gcc/ChangeLog:
* config/aarch64/aarch64.md (*adds_mul_imm_<mode>): Delete.
(*subs_mul_imm_<mode>): Delete.
(*adds_<optab><mode>_multp2): Delete.
(*subs_<optab><mode>_multp2): Delete.
(*add_mul_imm_<mode>): Delete.
(*add_<optab><ALLX:mode>_mult_<GPI:mode>): Delete.
(*add_<optab><SHORT:mode>_mult_si_uxtw): Delete.
(*add_<optab><mode>_multp2): Delete.
(*add_<optab>si_multp2_uxtw): Delete.
(*add_uxt<mode>_multp2): Delete.
(*add_uxtsi_multp2_uxtw): Delete.
(*sub_mul_imm_<mode>): Delete.
(*sub_mul_imm_si_uxtw): Delete.
(*sub_<optab><mode>_multp2): Delete.
(*sub_<optab>si_multp2_uxtw): Delete.
(*sub_uxt<mode>_multp2): Delete.
(*sub_uxtsi_multp2_uxtw): Delete.
(*neg_mul_imm_<mode>2): Delete.
(*neg_mul_imm_si2_uxtw): Delete.
* config/aarch64/predicates.md (aarch64_pwr_imm3): Delete.
(aarch64_pwr_2_si): Delete.
(aarch64_pwr_2_di): Delete.
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 9b20dd0b1a0..59516db4b77 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -2341,38 +2341,6 @@
[(set_attr "type" "alus_shift_imm")]
)
-(define_insn "*adds_mul_imm_<mode>"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
- (plus:GPI (mult:GPI
- (match_operand:GPI 1 "register_operand" "r")
- (match_operand:QI 2 "aarch64_pwr_2_<mode>" "n"))
- (match_operand:GPI 3 "register_operand" "r"))
- (const_int 0)))
- (set (match_operand:GPI 0 "register_operand" "=r")
- (plus:GPI (mult:GPI (match_dup 1) (match_dup 2))
- (match_dup 3)))]
- ""
- "adds\\t%<w>0, %<w>3, %<w>1, lsl %p2"
- [(set_attr "type" "alus_shift_imm")]
-)
-
-(define_insn "*subs_mul_imm_<mode>"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
- (minus:GPI (match_operand:GPI 1 "register_operand" "r")
- (mult:GPI
- (match_operand:GPI 2 "register_operand" "r")
- (match_operand:QI 3 "aarch64_pwr_2_<mode>" "n")))
- (const_int 0)))
- (set (match_operand:GPI 0 "register_operand" "=r")
- (minus:GPI (match_dup 1)
- (mult:GPI (match_dup 2) (match_dup 3))))]
- ""
- "subs\\t%<w>0, %<w>1, %<w>2, lsl %p3"
- [(set_attr "type" "alus_shift_imm")]
-)
-
(define_insn "*adds_<optab><ALLX:mode>_<GPI:mode>"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
@@ -2437,46 +2405,6 @@
[(set_attr "type" "alus_ext")]
)
-(define_insn "*adds_<optab><mode>_multp2"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
- (plus:GPI (ANY_EXTRACT:GPI
- (mult:GPI (match_operand:GPI 1 "register_operand" "r")
- (match_operand 2 "aarch64_pwr_imm3" "Up3"))
- (match_operand 3 "const_int_operand" "n")
- (const_int 0))
- (match_operand:GPI 4 "register_operand" "rk"))
- (const_int 0)))
- (set (match_operand:GPI 0 "register_operand" "=r")
- (plus:GPI (ANY_EXTRACT:GPI (mult:GPI (match_dup 1) (match_dup 2))
- (match_dup 3)
- (const_int 0))
- (match_dup 4)))]
- "aarch64_is_extend_from_extract (<MODE>mode, operands[2], operands[3])"
- "adds\\t%<w>0, %<w>4, %<w>1, <su>xt%e3 %p2"
- [(set_attr "type" "alus_ext")]
-)
-
-(define_insn "*subs_<optab><mode>_multp2"
- [(set (reg:CC_NZ CC_REGNUM)
- (compare:CC_NZ
- (minus:GPI (match_operand:GPI 4 "register_operand" "rk")
- (ANY_EXTRACT:GPI
- (mult:GPI (match_operand:GPI 1 "register_operand" "r")
- (match_operand 2 "aarch64_pwr_imm3" "Up3"))
- (match_operand 3 "const_int_operand" "n")
- (const_int 0)))
- (const_int 0)))
- (set (match_operand:GPI 0 "register_operand" "=r")
- (minus:GPI (match_dup 4) (ANY_EXTRACT:GPI
- (mult:GPI (match_dup 1) (match_dup 2))
- (match_dup 3)
- (const_int 0))))]
- "aarch64_is_extend_from_extract (<MODE>mode, operands[2], operands[3])"
- "subs\\t%<w>0, %<w>4, %<w>1, <su>xt%e3 %p2"
- [(set_attr "type" "alus_ext")]
-)
-
(define_insn "*add<mode>3nr_compare0"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
@@ -2534,16 +2462,6 @@
[(set_attr "type" "alu_shift_imm")]
)
-(define_insn "*add_mul_imm_<mode>"
- [(set (match_operand:GPI 0 "register_operand" "=r")
- (plus:GPI (mult:GPI (match_operand:GPI 1 "register_operand" "r")
- (match_operand:QI 2 "aarch64_pwr_2_<mode>" "n"))
- (match_operand:GPI 3 "register_operand" "r")))]
- ""
- "add\\t%<w>0, %<w>3, %<w>1, lsl %p2"
- [(set_attr "type" "alu_shift_imm")]
-)
-
(define_insn "*add_<optab><ALLX:mode>_<GPI:mode>"
[(set (match_operand:GPI 0 "register_operand" "=rk")
(plus:GPI (ANY_EXTEND:GPI (match_operand:ALLX 1 "register_operand" "r"))
@@ -2588,57 +2506,6 @@
[(set_attr "type" "alu_ext")]
)
-(define_insn "*add_<optab><ALLX:mode>_mult_<GPI:mode>"
- [(set (match_operand:GPI 0 "register_operand" "=rk")
- (plus:GPI (mult:GPI (ANY_EXTEND:GPI
- (match_operand:ALLX 1 "register_operand" "r"))
- (match_operand 2 "aarch64_pwr_imm3" "Up3"))
- (match_operand:GPI 3 "register_operand" "r")))]
- ""
- "add\\t%<GPI:w>0, %<GPI:w>3, %<GPI:w>1, <su>xt<ALLX:size> %p2"
- [(set_attr "type" "alu_ext")]
-)
-
-;; zero_extend version of above
-(define_insn "*add_<optab><SHORT:mode>_mult_si_uxtw"
- [(set (match_operand:DI 0 "register_operand" "=rk")
- (zero_extend:DI (plus:SI (mult:SI (ANY_EXTEND:SI
- (match_operand:SHORT 1 "register_operand" "r"))
- (match_operand 2 "aarch64_pwr_imm3" "Up3"))
- (match_operand:SI 3 "register_operand" "r"))))]
- ""
- "add\\t%w0, %w3, %w1, <su>xt<SHORT:size> %p2"
- [(set_attr "type" "alu_ext")]
-)
-
-(define_insn "*add_<optab><mode>_multp2"
- [(set (match_operand:GPI 0 "register_operand" "=rk")
- (plus:GPI (ANY_EXTRACT:GPI
- (mult:GPI (match_operand:GPI 1 "register_operand" "r")
- (match_operand 2 "aarch64_pwr_imm3" "Up3"))
- (match_operand 3 "const_int_operand" "n")
- (const_int 0))
- (match_operand:GPI 4 "register_operand" "r")))]
- "aarch64_is_extend_from_extract (<MODE>mode, operands[2], operands[3])"
- "add\\t%<w>0, %<w>4, %<w>1, <su>xt%e3 %p2"
- [(set_attr "type" "alu_ext")]
-)
-
-;; zero_extend version of above
-(define_insn "*add_<optab>si_multp2_uxtw"
- [(set (match_operand:DI 0 "register_operand" "=rk")
- (zero_extend:DI
- (plus:SI (ANY_EXTRACT:SI
- (mult:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand 2 "aarch64_pwr_imm3" "Up3"))
- (match_operand 3 "const_int_operand" "n")
- (const_int 0))
- (match_operand:SI 4 "register_operand" "r"))))]
- "aarch64_is_extend_from_extract (SImode, operands[2], operands[3])"
- "add\\t%w0, %w4, %w1, <su>xt%e3 %p2"
- [(set_attr "type" "alu_ext")]
-)
-
(define_expand "add<mode>3_carryin"
[(set (match_operand:GPI 0 "register_operand")
(plus:GPI
@@ -2840,38 +2707,6 @@
[(set_attr "type" "alu_ext")]
)
-(define_insn "*add_uxt<mode>_multp2"
- [(set (match_operand:GPI 0 "register_operand" "=rk")
- (plus:GPI (and:GPI
- (mult:GPI (match_operand:GPI 1 "register_operand" "r")
- (match_operand 2 "aarch64_pwr_imm3" "Up3"))
- (match_operand 3 "const_int_operand" "n"))
- (match_operand:GPI 4 "register_operand" "r")))]
- "aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), INTVAL (operands[3]))
!= 0"
- "*
- operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])),
- INTVAL (operands[3])));
- return \"add\t%<w>0, %<w>4, %<w>1, uxt%e3 %p2\";"
- [(set_attr "type" "alu_ext")]
-)
-
-;; zero_extend version of above
-(define_insn "*add_uxtsi_multp2_uxtw"
- [(set (match_operand:DI 0 "register_operand" "=rk")
- (zero_extend:DI
- (plus:SI (and:SI
- (mult:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand 2 "aarch64_pwr_imm3" "Up3"))
- (match_operand 3 "const_int_operand" "n"))
- (match_operand:SI 4 "register_operand" "r"))))]
- "aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), INTVAL (operands[3]))
!= 0"
- "*
- operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])),
- INTVAL (operands[3])));
- return \"add\t%w0, %w4, %w1, uxt%e3 %p2\";"
- [(set_attr "type" "alu_ext")]
-)
-
(define_insn "subsi3"
[(set (match_operand:SI 0 "register_operand" "=rk")
(minus:SI (match_operand:SI 1 "register_operand" "rk")
@@ -3275,30 +3110,6 @@
[(set_attr "type" "alu_shift_imm")]
)
-(define_insn "*sub_mul_imm_<mode>"
- [(set (match_operand:GPI 0 "register_operand" "=r")
- (minus:GPI (match_operand:GPI 3 "register_operand" "r")
- (mult:GPI
- (match_operand:GPI 1 "register_operand" "r")
- (match_operand:QI 2 "aarch64_pwr_2_<mode>" "n"))))]
- ""
- "sub\\t%<w>0, %<w>3, %<w>1, lsl %p2"
- [(set_attr "type" "alu_shift_imm")]
-)
-
-;; zero_extend version of above
-(define_insn "*sub_mul_imm_si_uxtw"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI
- (minus:SI (match_operand:SI 3 "register_operand" "r")
- (mult:SI
- (match_operand:SI 1 "register_operand" "r")
- (match_operand:QI 2 "aarch64_pwr_2_si" "n")))))]
- ""
- "sub\\t%w0, %w3, %w1, lsl %p2"
- [(set_attr "type" "alu_shift_imm")]
-)
-
(define_insn "*sub_<optab><ALLX:mode>_<GPI:mode>"
[(set (match_operand:GPI 0 "register_operand" "=rk")
(minus:GPI (match_operand:GPI 1 "register_operand" "rk")
@@ -3345,34 +3156,6 @@
[(set_attr "type" "alu_ext")]
)
-(define_insn "*sub_<optab><mode>_multp2"
- [(set (match_operand:GPI 0 "register_operand" "=rk")
- (minus:GPI (match_operand:GPI 4 "register_operand" "rk")
- (ANY_EXTRACT:GPI
- (mult:GPI (match_operand:GPI 1 "register_operand" "r")
- (match_operand 2 "aarch64_pwr_imm3" "Up3"))
- (match_operand 3 "const_int_operand" "n")
- (const_int 0))))]
- "aarch64_is_extend_from_extract (<MODE>mode, operands[2], operands[3])"
- "sub\\t%<w>0, %<w>4, %<w>1, <su>xt%e3 %p2"
- [(set_attr "type" "alu_ext")]
-)
-
-;; zero_extend version of above
-(define_insn "*sub_<optab>si_multp2_uxtw"
- [(set (match_operand:DI 0 "register_operand" "=rk")
- (zero_extend:DI
- (minus:SI (match_operand:SI 4 "register_operand" "rk")
- (ANY_EXTRACT:SI
- (mult:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand 2 "aarch64_pwr_imm3" "Up3"))
- (match_operand 3 "const_int_operand" "n")
- (const_int 0)))))]
- "aarch64_is_extend_from_extract (SImode, operands[2], operands[3])"
- "sub\\t%w0, %w4, %w1, <su>xt%e3 %p2"
- [(set_attr "type" "alu_ext")]
-)
-
;; The hardware description is op1 + ~op2 + C.
;; = op1 + (-op2 + 1) + (1 - !C)
;; = op1 - op2 - 1 + 1 - !C
@@ -3628,38 +3411,6 @@
[(set_attr "type" "alu_ext")]
)
-(define_insn "*sub_uxt<mode>_multp2"
- [(set (match_operand:GPI 0 "register_operand" "=rk")
- (minus:GPI (match_operand:GPI 4 "register_operand" "rk")
- (and:GPI
- (mult:GPI (match_operand:GPI 1 "register_operand" "r")
- (match_operand 2 "aarch64_pwr_imm3" "Up3"))
- (match_operand 3 "const_int_operand" "n"))))]
- "aarch64_uxt_size (exact_log2 (INTVAL (operands[2])),INTVAL (operands[3]))
!= 0"
- "*
- operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])),
- INTVAL (operands[3])));
- return \"sub\t%<w>0, %<w>4, %<w>1, uxt%e3 %p2\";"
- [(set_attr "type" "alu_ext")]
-)
-
-;; zero_extend version of above
-(define_insn "*sub_uxtsi_multp2_uxtw"
- [(set (match_operand:DI 0 "register_operand" "=rk")
- (zero_extend:DI
- (minus:SI (match_operand:SI 4 "register_operand" "rk")
- (and:SI
- (mult:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand 2 "aarch64_pwr_imm3" "Up3"))
- (match_operand 3 "const_int_operand" "n")))))]
- "aarch64_uxt_size (exact_log2 (INTVAL (operands[2])),INTVAL (operands[3]))
!= 0"
- "*
- operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])),
- INTVAL (operands[3])));
- return \"sub\t%w0, %w4, %w1, uxt%e3 %p2\";"
- [(set_attr "type" "alu_ext")]
-)
-
(define_expand "abs<mode>2"
[(match_operand:GPI 0 "register_operand")
(match_operand:GPI 1 "register_operand")]
@@ -3772,28 +3523,6 @@
[(set_attr "type" "alu_shift_imm")]
)
-(define_insn "*neg_mul_imm_<mode>2"
- [(set (match_operand:GPI 0 "register_operand" "=r")
- (neg:GPI (mult:GPI
- (match_operand:GPI 1 "register_operand" "r")
- (match_operand:QI 2 "aarch64_pwr_2_<mode>" "n"))))]
- ""
- "neg\\t%<w>0, %<w>1, lsl %p2"
- [(set_attr "type" "alu_shift_imm")]
-)
-
-;; zero_extend version of above
-(define_insn "*neg_mul_imm_si2_uxtw"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI
- (neg:SI (mult:SI
- (match_operand:SI 1 "register_operand" "r")
- (match_operand:QI 2 "aarch64_pwr_2_si" "n")))))]
- ""
- "neg\\t%w0, %w1, lsl %p2"
- [(set_attr "type" "alu_shift_imm")]
-)
-
(define_insn "mul<mode>3"
[(set (match_operand:GPI 0 "register_operand" "=r")
(mult:GPI (match_operand:GPI 1 "register_operand" "r")
diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md
index 1754b1eff9f..91b51483f33 100644
--- a/gcc/config/aarch64/predicates.md
+++ b/gcc/config/aarch64/predicates.md
@@ -235,21 +235,6 @@
(and (match_code "const_int")
(match_test "IN_RANGE (UINTVAL (op), 0, 0xffffff)")))
-(define_predicate "aarch64_pwr_imm3"
- (and (match_code "const_int")
- (match_test "INTVAL (op) != 0
- && (unsigned) exact_log2 (INTVAL (op)) <= 4")))
-
-(define_predicate "aarch64_pwr_2_si"
- (and (match_code "const_int")
- (match_test "INTVAL (op) != 0
- && (unsigned) exact_log2 (INTVAL (op)) < 32")))
-
-(define_predicate "aarch64_pwr_2_di"
- (and (match_code "const_int")
- (match_test "INTVAL (op) != 0
- && (unsigned) exact_log2 (INTVAL (op)) < 64")))
-
(define_predicate "aarch64_mem_pair_offset"
(and (match_code "const_int")
(match_test "aarch64_offset_7bit_signed_scaled_p (mode, INTVAL (op))")))
