On Mon, Nov 9, 2020 at 11:15 PM Monk Chiang <monk.chi...@sifive.com> wrote:
> diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h > index 172c7ca7c98..3bd1993c4c9 100644 > --- a/gcc/config/riscv/riscv.h > +++ b/gcc/config/riscv/riscv.h > @@ -342,9 +342,13 @@ extern const char *riscv_default_mtune (int argc, > const char **argv); > The epilogue temporary mustn't conflict with the return registers, > the frame pointer, the EH stack adjustment, or the EH data registers. > */ > > -#define RISCV_PROLOGUE_TEMP_REGNUM (GP_TEMP_FIRST + 1) > +#define RISCV_PROLOGUE_TEMP_REGNUM (GP_TEMP_FIRST) > #define RISCV_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, > RISCV_PROLOGUE_TEMP_REGNUM) > > +#define RISCV_CALL_ADDRESS_TEMP_REGNUM (GP_TEMP_FIRST + 1) > +#define RISCV_CALL_ADDRESS_TEMP(MODE) \ > + gen_rtx_REG (MODE, RISCV_CALL_ADDRESS_TEMP_REGNUM) > This looks generally OK, however there is a minor problem that we have code in riscv_compute_frame_info to save t1 in an interrupt handler register with a large stack frame, as we know the prologue code will clobber t1 in this case. However, with this patch, the prologue now clobbers t0 instead. So riscv_computer_frame_info needs to be fixed. I'd suggest changing the T1_REGNUM to RISCV_PROLOGUE_TEMP_REGNUM to prevent this from happening again, that is probably my fault. And the interrupt_save_t1 variable should be renamed, maybe to interupt_save_prologue_temp. You can see the problem with gcc/testsuite/gcc.target/riscv/interrupt-3.c if you compile with -O0 and we get foo: addi sp,sp,-32 sw t1,28(sp) sw s0,24(sp) addi s0,sp,32 li t0,-4096 addi t0,t0,16 add sp,sp,t0 so we are saving t1 and then clobbering t0 with your patch. Otherwise this looks good. Jim
