Hi all,
I'd like to submit the following simple patch to clean some Low Loop
Overhead test failing on hard float configurations.
lob2.c and lob5.c are failing with: "'-mfloat-abi=hard': selected
processor lacks an FPU".
lob3.c and lob5.c got "-mfloat-abi=soft and -mfloat-abi=hard may not
be used together".
Okay for trunk?
Thanks
Andrea
>From ac47dfed0230d9fe596d27331b04ef194633927d Mon Sep 17 00:00:00 2001
From: Andrea Corallo <andrea.cora...@arm.com>
Date: Thu, 26 Nov 2020 12:33:18 +0100
Subject: [PATCH] arm: [testsuite] fix lob tests for -mfloat-abi=hard
2020-11-26 Andrea Corallo <andrea.cora...@arm.com>
* gcc.target/arm/lob2.c: Add '-mfpu=fp-armv8' flag.
* gcc.target/arm/lob3.c: Skip with '-mfloat-abi=hard'.
* gcc.target/arm/lob4.c: Likewise.
* gcc.target/arm/lob5.c: Add '-mfpu=fp-armv8' flag.
---
gcc/testsuite/gcc.target/arm/lob2.c | 2 +-
gcc/testsuite/gcc.target/arm/lob3.c | 2 +-
gcc/testsuite/gcc.target/arm/lob4.c | 2 +-
gcc/testsuite/gcc.target/arm/lob5.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.target/arm/lob2.c
b/gcc/testsuite/gcc.target/arm/lob2.c
index fdeb2686f51..2a7e2fd3d89 100644
--- a/gcc/testsuite/gcc.target/arm/lob2.c
+++ b/gcc/testsuite/gcc.target/arm/lob2.c
@@ -2,7 +2,7 @@
if a non-inlineable function call takes place inside the loop. */
/* { dg-do compile } */
/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
-/* { dg-options "-march=armv8.1-m.main -mthumb -O3 --save-temps" } */
+/* { dg-options "-march=armv8.1-m.main -mfpu=fp-armv8 -mthumb -O3
--save-temps" } */
#include <stdlib.h>
#include "lob.h"
diff --git a/gcc/testsuite/gcc.target/arm/lob3.c
b/gcc/testsuite/gcc.target/arm/lob3.c
index 70314ea84b3..f5290063f28 100644
--- a/gcc/testsuite/gcc.target/arm/lob3.c
+++ b/gcc/testsuite/gcc.target/arm/lob3.c
@@ -1,7 +1,7 @@
/* Check that GCC does not generate Armv8.1-M low over head loop instructions
if causes VFP emulation library calls to happen inside the loop. */
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" "-mfloat-abi=hard" } } */
/* { dg-options "-march=armv8.1-m.main -mthumb -O3 --save-temps
-mfloat-abi=soft" } */
/* { dg-require-effective-target arm_softfloat } */
#include <stdlib.h>
diff --git a/gcc/testsuite/gcc.target/arm/lob4.c
b/gcc/testsuite/gcc.target/arm/lob4.c
index 792f352d682..86c774e1b57 100644
--- a/gcc/testsuite/gcc.target/arm/lob4.c
+++ b/gcc/testsuite/gcc.target/arm/lob4.c
@@ -1,7 +1,7 @@
/* Check that GCC does not generate Armv8.1-M low over head loop instructions
if LR is modified within the loop. */
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" "-mfloat-abi=hard" } } */
/* { dg-options "-march=armv8.1-m.main -mthumb -O3 --save-temps
-mfloat-abi=soft" } */
/* { dg-require-effective-target arm_softfloat } */
#include <stdlib.h>
diff --git a/gcc/testsuite/gcc.target/arm/lob5.c
b/gcc/testsuite/gcc.target/arm/lob5.c
index 1a6adf1e28e..ea8523d3c77 100644
--- a/gcc/testsuite/gcc.target/arm/lob5.c
+++ b/gcc/testsuite/gcc.target/arm/lob5.c
@@ -3,7 +3,7 @@
therefore is not optimizable. Outer loops are not optimized. */
/* { dg-do compile } */
/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
-/* { dg-options "-march=armv8.1-m.main -mthumb -O3 --save-temps" } */
+/* { dg-options "-march=armv8.1-m.main -mfpu=fp-armv8 -mthumb -O3
--save-temps" } */
#include <stdlib.h>
#include "lob.h"
--
2.20.1
