diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index a71ae4d724136c8b626d397bf6187e8b595a2b8a..13bc6928d4de83513bc9d92e9429fdff90565100 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -188,6 +188,9 @@ /* Implemented by aarch64_mls_n. */ BUILTIN_VDQHS (TERNOP, mls_n, 0, NONE) + /* Implemented by aarch64_shrn". */ + BUILTIN_VQN (SHIFTIMM, shrn, 0, NONE) + /* Implemented by aarch64_mlsl. */ BUILTIN_VD_BHSI (TERNOP, smlsl, 0, NONE) BUILTIN_VD_BHSI (TERNOPU, umlsl, 0, NONE) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index db56b61baf2093c88d8757b25580b3032f00a355..872aa83fc926dfa449223f6fdd116e1b2af436dd 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1679,6 +1679,56 @@ (define_expand "vec_pack_trunc_" DONE; }) +(define_insn "aarch64_shrn_insn_le" + [(set (match_operand: 0 "register_operand" "=w") + (vec_concat: + (truncate: + (lshiftrt:VQN (match_operand:VQN 1 "register_operand" "w") + (match_operand:VQN 2 "aarch64_simd_rshift_imm"))) + (match_operand: 3 "aarch64_simd_or_scalar_imm_zero")))] + "TARGET_SIMD && !BYTES_BIG_ENDIAN" + "shrn\\t%0., %1., %2" + [(set_attr "type" "neon_shift_imm_narrow_q")] +) + +(define_insn "aarch64_shrn_insn_be" + [(set (match_operand: 0 "register_operand" "=w") + (vec_concat: + (match_operand: 3 "aarch64_simd_or_scalar_imm_zero") + (truncate: + (lshiftrt:VQN (match_operand:VQN 1 "register_operand" "w") + (match_operand:VQN 2 "aarch64_simd_rshift_imm")))))] + "TARGET_SIMD && BYTES_BIG_ENDIAN" + "shrn\\t%0., %1., %2" + [(set_attr "type" "neon_shift_imm_narrow_q")] +) + +(define_expand "aarch64_shrn" + [(set (match_operand: 0 "register_operand") + (truncate: + (lshiftrt:VQN (match_operand:VQN 1 "register_operand") + (match_operand:SI 2 "aarch64_simd_shift_imm_offset_"))))] + "TARGET_SIMD" + { + operands[2] = aarch64_simd_gen_const_vector_dup (mode, + INTVAL (operands[2])); + rtx tmp = gen_reg_rtx (mode); + if (BYTES_BIG_ENDIAN) + emit_insn (gen_aarch64_shrn_insn_be (tmp, operands[1], + operands[2], CONST0_RTX (mode))); + else + emit_insn (gen_aarch64_shrn_insn_le (tmp, operands[1], + operands[2], CONST0_RTX (mode))); + + /* The intrinsic expects a narrow result, so emit a subreg that will get + optimized away as appropriate. */ + emit_move_insn (operands[0], lowpart_subreg (mode, tmp, + mode)); + DONE; + } +) + + ;; For quads. (define_insn "vec_pack_trunc_" diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index b5c1f062bbcdf2185fef65863c84f4997bc97d03..80d75555a71817637035bf25b3a5cccd87947242 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -8584,6 +8584,47 @@ vmovn_u64 (uint64x2_t __a) return (uint32x2_t) __builtin_aarch64_xtnv2di ((int64x2_t) __a); } +__extension__ extern __inline int8x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vshrn_n_s16 (int16x8_t __a, const int __b) +{ + return __builtin_aarch64_shrnv8hi (__a, __b); +} + +__extension__ extern __inline int16x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vshrn_n_s32 (int32x4_t __a, const int __b) +{ + return __builtin_aarch64_shrnv4si (__a, __b); +} + +__extension__ extern __inline int32x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vshrn_n_s64 (int64x2_t __a, const int __b) +{ + return __builtin_aarch64_shrnv2di (__a, __b); +} + +__extension__ extern __inline uint8x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vshrn_n_u16 (uint16x8_t __a, const int __b) +{ + return (uint8x8_t)__builtin_aarch64_shrnv8hi ((int16x8_t)__a, __b); +} + +__extension__ extern __inline uint16x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vshrn_n_u32 (uint32x4_t __a, const int __b) +{ + return (uint16x4_t)__builtin_aarch64_shrnv4si ((int32x4_t)__a, __b); +} + +__extension__ extern __inline uint32x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vshrn_n_u64 (uint64x2_t __a, const int __b) +{ + return (uint32x2_t)__builtin_aarch64_shrnv2di ((int64x2_t)__a, __b); +} #define vmull_high_lane_s16(a, b, c) \ __extension__ \ ({ \ @@ -9858,78 +9899,6 @@ vrsqrteq_u32 (uint32x4_t __a) result; \ }) -#define vshrn_n_s16(a, b) \ - __extension__ \ - ({ \ - int16x8_t a_ = (a); \ - int8x8_t result; \ - __asm__ ("shrn %0.8b,%1.8h,%2" \ - : "=w"(result) \ - : "w"(a_), "i"(b) \ - : /* No clobbers */); \ - result; \ - }) - -#define vshrn_n_s32(a, b) \ - __extension__ \ - ({ \ - int32x4_t a_ = (a); \ - int16x4_t result; \ - __asm__ ("shrn %0.4h,%1.4s,%2" \ - : "=w"(result) \ - : "w"(a_), "i"(b) \ - : /* No clobbers */); \ - result; \ - }) - -#define vshrn_n_s64(a, b) \ - __extension__ \ - ({ \ - int64x2_t a_ = (a); \ - int32x2_t result; \ - __asm__ ("shrn %0.2s,%1.2d,%2" \ - : "=w"(result) \ - : "w"(a_), "i"(b) \ - : /* No clobbers */); \ - result; \ - }) - -#define vshrn_n_u16(a, b) \ - __extension__ \ - ({ \ - uint16x8_t a_ = (a); \ - uint8x8_t result; \ - __asm__ ("shrn %0.8b,%1.8h,%2" \ - : "=w"(result) \ - : "w"(a_), "i"(b) \ - : /* No clobbers */); \ - result; \ - }) - -#define vshrn_n_u32(a, b) \ - __extension__ \ - ({ \ - uint32x4_t a_ = (a); \ - uint16x4_t result; \ - __asm__ ("shrn %0.4h,%1.4s,%2" \ - : "=w"(result) \ - : "w"(a_), "i"(b) \ - : /* No clobbers */); \ - result; \ - }) - -#define vshrn_n_u64(a, b) \ - __extension__ \ - ({ \ - uint64x2_t a_ = (a); \ - uint32x2_t result; \ - __asm__ ("shrn %0.2s,%1.2d,%2" \ - : "=w"(result) \ - : "w"(a_), "i"(b) \ - : /* No clobbers */); \ - result; \ - }) - #define vsli_n_p8(a, b, c) \ __extension__ \ ({ \ diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 555a0b2255571c35e03970046bf062d7e2162dcf..4f0b281e7df6e8976dccb5dfb01a25f460796c60 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -1458,6 +1458,9 @@ (define_mode_attr ve_mode [(V8QI "qi") (V16QI "qi") (QI "qi") (HI "hi") (SI "si")]) +;; Like ve_mode but for the half-width modes. +(define_mode_attr vn_mode [(V8HI "qi") (V4SI "hi") (V2DI "si")]) + ;; Vm for lane instructions is restricted to FP_LO_REGS. (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x") (V2SI "w") (V4SI "w") (SI "w")])