On Fri, 29 Jan 2021 at 16:03, Kyrylo Tkachov <[email protected]> wrote:
>
>
>
> > -----Original Message-----
> > From: Gcc-patches <[email protected]> On Behalf Of
> > Christophe Lyon via Gcc-patches
> > Sent: 29 January 2021 14:55
> > To: [email protected]
> > Subject: [PATCH] arm: Auto-vectorization for MVE: vorn
> >
> > This patch enables MVE vornq instructions for auto-vectorization. MVE
> > vornq insns in mve.md are modified to use ior instead of unspec
> > expression to support ior<mode>3. The ior<mode>3 expander is added to
> > vec-common.md
> >
> > 2021-01-29 Christophe Lyon <[email protected]>
> >
> > gcc/
> > * config/arm/iterators.md (supf): Remove VORNQ_S and VORNQ_U.
> > (VORNQ): Remove.
> > * config/arm/mve.md (mve_vornq_s<mode>): New entry for vorn
> > instruction using expression ior.
> > (mve_vornq_u<mode>): New expander.
> > (mve_vornq_f<mode>): Use ior code instead of unspec.
> > * config/arm/unspecs.md (VORNQ_S, VORNQ_U, VORNQ_F):
> > Remove.
> > * config/arm/vec-common.md (orn<mode>3): New expander.
> >
> > gcc/testsuite/
> > * gcc.target/arm/simd/mve-vorn.c: Add vorn tests.
> > ---
> > gcc/config/arm/iterators.md | 3 +--
> > gcc/config/arm/mve.md | 23 +++++++++++------
> > gcc/config/arm/unspecs.md | 3 ---
> > gcc/config/arm/vec-common.md | 8 ++++++
> > gcc/testsuite/gcc.target/arm/simd/mve-vorn.c | 38
> > ++++++++++++++++++++++++++++
> > 5 files changed, 62 insertions(+), 13 deletions(-)
> > create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vorn.c
> >
> > diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
> > index b902790..43aab23 100644
> > --- a/gcc/config/arm/iterators.md
> > +++ b/gcc/config/arm/iterators.md
> > @@ -1293,7 +1293,7 @@ (define_int_attr supf [(VCVTQ_TO_F_S "s")
> > (VCVTQ_TO_F_U "u") (VREV16Q_S "s")
> > (VMULLBQ_INT_S "s") (VMULLBQ_INT_U "u")
> > (VQADDQ_S "s")
> > (VMULLTQ_INT_S "s") (VMULLTQ_INT_U "u")
> > (VQADDQ_U "u")
> > (VMULQ_N_S "s") (VMULQ_N_U "u") (VMULQ_S "s")
> > - (VMULQ_U "u") (VORNQ_S "s") (VORNQ_U "u")
> > + (VMULQ_U "u")
> > (VQADDQ_N_S "s") (VQADDQ_N_U "u")
> > (VQRSHLQ_N_S "s") (VQRSHLQ_N_U "u") (VQRSHLQ_S
> > "s")
> > (VQRSHLQ_U "u") (VQSHLQ_N_S "s")
> > (VQSHLQ_N_U "u")
> > @@ -1563,7 +1563,6 @@ (define_int_iterator VMULLBQ_INT
> > [VMULLBQ_INT_U VMULLBQ_INT_S])
> > (define_int_iterator VMULLTQ_INT [VMULLTQ_INT_U VMULLTQ_INT_S])
> > (define_int_iterator VMULQ [VMULQ_U VMULQ_S])
> > (define_int_iterator VMULQ_N [VMULQ_N_U VMULQ_N_S])
> > -(define_int_iterator VORNQ [VORNQ_U VORNQ_S])
> > (define_int_iterator VQADDQ [VQADDQ_U VQADDQ_S])
> > (define_int_iterator VQADDQ_N [VQADDQ_N_S VQADDQ_N_U])
> > (define_int_iterator VQRSHLQ [VQRSHLQ_S VQRSHLQ_U])
> > diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
> > index 465f71c..ec0ef7b 100644
> > --- a/gcc/config/arm/mve.md
> > +++ b/gcc/config/arm/mve.md
> > @@ -1634,18 +1634,26 @@ (define_insn "mve_vmulq<mode>"
> > ;;
> > ;; [vornq_u, vornq_s])
> > ;;
> > -(define_insn "mve_vornq_<supf><mode>"
> > +(define_insn "mve_vornq_s<mode>"
> > [
> > (set (match_operand:MVE_2 0 "s_register_operand" "=w")
> > - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
> > - (match_operand:MVE_2 2 "s_register_operand" "w")]
> > - VORNQ))
> > + (ior:MVE_2 (not:MVE_2 (match_operand:MVE_2 2
> > "s_register_operand" "w"))
> > + (match_operand:MVE_2 1 "s_register_operand" "w")))
> > ]
> > "TARGET_HAVE_MVE"
> > - "vorn %q0, %q1, %q2"
> > + "vorn\t%q0, %q1, %q2"
> > [(set_attr "type" "mve_move")
> > ])
> >
> > +(define_expand "mve_vornq_u<mode>"
> > + [
> > + (set (match_operand:MVE_2 0 "s_register_operand")
> > + (ior:MVE_2 (not:MVE_2 (match_operand:MVE_2 2
> > "s_register_operand"))
> > + (match_operand:MVE_2 1 "s_register_operand")))
> > + ]
> > + "TARGET_HAVE_MVE"
> > +)
> > +
> > ;;
> > ;; [vorrq_s, vorrq_u])
> > ;;
> > @@ -2630,9 +2638,8 @@ (define_insn "mve_vmulq_n_f<mode>"
> > (define_insn "mve_vornq_f<mode>"
> > [
> > (set (match_operand:MVE_0 0 "s_register_operand" "=w")
> > - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
> > - (match_operand:MVE_0 2 "s_register_operand" "w")]
> > - VORNQ_F))
> > + (ior:MVE_0 (not:MVE_0 (match_operand:MVE_0 2
> > "s_register_operand" "w"))
> > + (match_operand:MVE_0 1 "s_register_operand" "w")))
> > ]
> > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> > "vorn %q0, %q1, %q2"
> > diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md
> > index c6ebb6f..4d47ab7 100644
> > --- a/gcc/config/arm/unspecs.md
> > +++ b/gcc/config/arm/unspecs.md
> > @@ -622,7 +622,6 @@ (define_c_enum "unspec" [
> > VMULLTQ_INT_S
> > VMULQ_S
> > VMULQ_N_S
> > - VORNQ_S
> > VQADDQ_S
> > VQADDQ_N_S
> > VQRSHLQ_S
> > @@ -663,7 +662,6 @@ (define_c_enum "unspec" [
> > VMULLTQ_INT_U
> > VMULQ_U
> > VMULQ_N_U
> > - VORNQ_U
> > VQADDQ_U
> > VQADDQ_N_U
> > VQRSHLQ_U
> > @@ -734,7 +732,6 @@ (define_c_enum "unspec" [
> > VMINNMVQ_F
> > VMULQ_F
> > VMULQ_N_F
> > - VORNQ_F
> > VSUBQ_F
> > VADDLVAQ_U
> > VADDLVAQ_S
> > diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-
> > common.md
> > index 692b28e..444e4f5 100644
> > --- a/gcc/config/arm/vec-common.md
> > +++ b/gcc/config/arm/vec-common.md
> > @@ -187,6 +187,14 @@ (define_expand "ior<mode>3"
> > "ARM_HAVE_<MODE>_ARITH"
> > )
> >
> > +(define_expand "orn<mode>3"
> > + [(set (match_operand:VDQ 0 "s_register_operand" "")
> > + (ior:VDQ (not:VDQ (match_operand:VDQ 2 "s_register_operand" ""))
> > + (match_operand:VDQ 1 "s_register_operand" "")
> > + ))]
> > + "ARM_HAVE_<MODE>_ARITH"
> > +)
>
> There's no standard name "orn" that is used by the midend, so I don't think
> this will ever be used.
> Does the vecorisation work without it?
Ha yes indeed, vectorization passes without the define_expand.
> Thanks,
> Kyrill
>
> > +
> > (define_expand "xor<mode>3"
> > [(set (match_operand:VDQ 0 "s_register_operand" "")
> > (xor:VDQ (match_operand:VDQ 1 "s_register_operand" "")
> > diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vorn.c
> > b/gcc/testsuite/gcc.target/arm/simd/mve-vorn.c
> > new file mode 100644
> > index 0000000..3f62d0a
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vorn.c
> > @@ -0,0 +1,38 @@
> > +/* { dg-do assemble } */
> > +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> > +/* { dg-add-options arm_v8_1m_mve } */
> > +/* { dg-additional-options "-O3" } */
> > +
> > +#include <stdint.h>
> > +
> > +#define FUNC(SIGN, TYPE, BITS, NB, OP, NAME)
> > \
> > + void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t *
> > __restrict__ dest, TYPE##BITS##_t *a, TYPE##BITS##_t *b) { \
> > + int i; \
> > + for (i=0; i<NB; i++) { \
> > + dest[i] = a[i] OP b[i];
> > \
> > + }
> > \
> > +}
> > +
> > +/* 64-bit vectors. */
> > +FUNC(s, int, 32, 2, | ~ , vorn)
> > +FUNC(u, uint, 32, 2, | ~ , vorn)
> > +FUNC(s, int, 16, 4, | ~ , vorn)
> > +FUNC(u, uint, 16, 4, | ~ , vorn)
> > +FUNC(s, int, 8, 8, | ~ , vorn)
> > +FUNC(u, uint, 8, 8, | ~ , vorn)
> > +
> > +/* 128-bit vectors. */
> > +FUNC(s, int, 32, 4, | ~ , vorn)
> > +FUNC(u, uint, 32, 4, | ~ , vorn)
> > +FUNC(s, int, 16, 8, | ~ , vorn)
> > +FUNC(u, uint, 16, 8, | ~ , vorn)
> > +FUNC(s, int, 8, 16, | ~ , vorn)
> > +FUNC(u, uint, 8, 16, | ~ , vorn)
> > +
> > +/* MVE has only 128-bit vectors, so we can vectorize only half of the
> > + functions above. */
> > +/* Although float16 and float32 types are supported at assembly level,
> > + we cannot test them with the '| ~ ' operator, so we check only the
> > + integer variants. */
> > +/* No need to test immediates as second operand, they are covered by vorn.
> > */
> > +/* { dg-final { scan-assembler-times {vorn\tq[0-9]+, q[0-9]+, q[0-9]+} 6 }
> > } */
> > --
> > 2.7.4
>
