On s390* the only missing part for the mentioned testcases was a load of
a double floating-point zero via a move (in particular for quite old
machines) which was added in commit 46c47420a5fefd4d9d02b0db347235dd74e20fb2.
Common code implementation is sufficient in order to clear volatile
GPRs, FPRs, and VRs. Access registers a0 and a1 are nonvolatile and not
cleared. Therefore, target hook TARGET_ZERO_CALL_USED_REGS is not
implemented for s390*.
Added a target specific test in order to ensure that all call clobbered
GPRs, FPRs, and VRs are zeroed and all call saved registers are kept.
Ok for mainline?
gcc/testsuite/ChangeLog:
* c-c++-common/zero-scratch-regs-8.c: Enable on s390*.
* c-c++-common/zero-scratch-regs-9.c: Likewise.
* c-c++-common/zero-scratch-regs-10.c: Likewise.
* c-c++-common/zero-scratch-regs-11.c: Likewise.
* gcc.target/s390/zero-scratch-regs-1.c: New test.
---
.../c-c++-common/zero-scratch-regs-10.c | 2 +-
.../c-c++-common/zero-scratch-regs-11.c | 2 +-
.../c-c++-common/zero-scratch-regs-8.c | 2 +-
.../c-c++-common/zero-scratch-regs-9.c | 2 +-
.../gcc.target/s390/zero-scratch-regs-1.c | 65 +++++++++++++++++++
5 files changed, 69 insertions(+), 4 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/s390/zero-scratch-regs-1.c
diff --git a/gcc/testsuite/c-c++-common/zero-scratch-regs-10.c
b/gcc/testsuite/c-c++-common/zero-scratch-regs-10.c
index ab17143bc4b..96e0b79b328 100644
--- a/gcc/testsuite/c-c++-common/zero-scratch-regs-10.c
+++ b/gcc/testsuite/c-c++-common/zero-scratch-regs-10.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-*
aarch64*-*-* nvptx*-*-* } } } */
+/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-*
aarch64*-*-* nvptx*-*-* s390*-*-* } } } */
/* { dg-options "-O2" } */
#include <assert.h>
diff --git a/gcc/testsuite/c-c++-common/zero-scratch-regs-11.c
b/gcc/testsuite/c-c++-common/zero-scratch-regs-11.c
index 6642a377798..0714f95a04f 100644
--- a/gcc/testsuite/c-c++-common/zero-scratch-regs-11.c
+++ b/gcc/testsuite/c-c++-common/zero-scratch-regs-11.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-*
aarch64*-*-* arm*-*-* nvptx*-*-* } } } */
+/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-*
aarch64*-*-* arm*-*-* nvptx*-*-* s390*-*-* } } } */
/* { dg-options "-O2 -fzero-call-used-regs=all" } */
#include "zero-scratch-regs-10.c"
diff --git a/gcc/testsuite/c-c++-common/zero-scratch-regs-8.c
b/gcc/testsuite/c-c++-common/zero-scratch-regs-8.c
index 867c6bdce2c..aceda7e5cb8 100644
--- a/gcc/testsuite/c-c++-common/zero-scratch-regs-8.c
+++ b/gcc/testsuite/c-c++-common/zero-scratch-regs-8.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-*
aarch64*-*-* arm*-*-* nvptx*-*-* } } } */
+/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-*
aarch64*-*-* arm*-*-* nvptx*-*-* s390*-*-* } } } */
/* { dg-options "-O2 -fzero-call-used-regs=all-arg" } */
#include "zero-scratch-regs-1.c"
diff --git a/gcc/testsuite/c-c++-common/zero-scratch-regs-9.c
b/gcc/testsuite/c-c++-common/zero-scratch-regs-9.c
index 4b45d7061df..f3152a7a732 100644
--- a/gcc/testsuite/c-c++-common/zero-scratch-regs-9.c
+++ b/gcc/testsuite/c-c++-common/zero-scratch-regs-9.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-*
aarch64*-*-* arm*-*-* nvptx*-*-* } } } */
+/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-*
aarch64*-*-* arm*-*-* nvptx*-*-* s390*-*-* } } } */
/* { dg-options "-O2 -fzero-call-used-regs=all" } */
#include "zero-scratch-regs-1.c"
diff --git a/gcc/testsuite/gcc.target/s390/zero-scratch-regs-1.c
b/gcc/testsuite/gcc.target/s390/zero-scratch-regs-1.c
new file mode 100644
index 00000000000..c394c4b69e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/zero-scratch-regs-1.c
@@ -0,0 +1,65 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fzero-call-used-regs=all -march=z13" } */
+
+/* Ensure that all call clobbered GPRs, FPRs, and VRs are zeroed and all call
+ saved registers are kept. */
+
+void foo (void) { }
+
+/* { dg-final { scan-assembler-times "lhi\t" 6 { target { ! lp64 } } } } */
+/* { dg-final { scan-assembler "lhi\t%r0,0" { target { ! lp64 } } } } */
+/* { dg-final { scan-assembler "lhi\t%r1,0" { target { ! lp64 } } } } */
+/* { dg-final { scan-assembler "lhi\t%r2,0" { target { ! lp64 } } } } */
+/* { dg-final { scan-assembler "lhi\t%r3,0" { target { ! lp64 } } } } */
+/* { dg-final { scan-assembler "lhi\t%r4,0" { target { ! lp64 } } } } */
+/* { dg-final { scan-assembler "lhi\t%r5,0" { target { ! lp64 } } } } */
+
+/* { dg-final { scan-assembler-times "lzdr\t" 14 { target { ! lp64 } } } } */
+/* { dg-final { scan-assembler "lzdr\t%f0" { target { ! lp64 } } } } */
+/* { dg-final { scan-assembler "lzdr\t%f1" { target { ! lp64 } } } } */
+/* { dg-final { scan-assembler "lzdr\t%f2" { target { ! lp64 } } } } */
+/* { dg-final { scan-assembler "lzdr\t%f3" { target { ! lp64 } } } } */
+/* { dg-final { scan-assembler "lzdr\t%f5" { target { ! lp64 } } } } */
+/* { dg-final { scan-assembler "lzdr\t%f7" { target { ! lp64 } } } } */
+/* { dg-final { scan-assembler "lzdr\t%f8" { target { ! lp64 } } } } */
+/* { dg-final { scan-assembler "lzdr\t%f9" { target { ! lp64 } } } } */
+/* { dg-final { scan-assembler "lzdr\t%f10" { target { ! lp64 } } } } */
+/* { dg-final { scan-assembler "lzdr\t%f11" { target { ! lp64 } } } } */
+/* { dg-final { scan-assembler "lzdr\t%f12" { target { ! lp64 } } } } */
+/* { dg-final { scan-assembler "lzdr\t%f13" { target { ! lp64 } } } } */
+/* { dg-final { scan-assembler "lzdr\t%f14" { target { ! lp64 } } } } */
+/* { dg-final { scan-assembler "lzdr\t%f15" { target { ! lp64 } } } } */
+
+/* { dg-final { scan-assembler-times "lghi\t" 6 { target { lp64 } } } } */
+/* { dg-final { scan-assembler "lghi\t%r0,0" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "lghi\t%r1,0" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "lghi\t%r2,0" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "lghi\t%r3,0" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "lghi\t%r4,0" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "lghi\t%r5,0" { target { lp64 } } } } */
+
+/* { dg-final { scan-assembler-times "vzero\t" 24 { target { lp64 } } } } */
+/* { dg-final { scan-assembler "vzero\t%v0" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "vzero\t%v1" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "vzero\t%v2" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "vzero\t%v3" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "vzero\t%v4" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "vzero\t%v5" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "vzero\t%v6" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "vzero\t%v7" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "vzero\t%v16" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "vzero\t%v17" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "vzero\t%v18" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "vzero\t%v19" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "vzero\t%v20" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "vzero\t%v21" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "vzero\t%v22" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "vzero\t%v23" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "vzero\t%v24" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "vzero\t%v25" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "vzero\t%v26" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "vzero\t%v27" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "vzero\t%v28" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "vzero\t%v29" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "vzero\t%v30" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "vzero\t%v31" { target { lp64 } } } } */
--
2.23.0
