[PATCH] i386: Add XOP comparisons for 4- and 8-byte vectors [PR100637]

[Uros Bizjak via Gcc-patches]

2021-05-27  Uroš Bizjak  <ubiz...@gmail.com>

gcc/
    PR target/100637
    * config/i386/i386-expand.c (ix86_expand_int_sse_cmp):
    For TARGET_XOP bypass SSE comparisons for all supported vector modes.
    * config/i386/mmx.md (*xop_maskcmp<MMXMODEI:mode>3): New insn pattern.
    (*xop_maskcmp<VI_32:mode>3): Ditto.
    (*xop_maskcmp_uns<MMXMODEI:mode>3): Ditto.
    (*xop_maskcmp_uns<VI_32:mode>3): Ditto.

Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.

Pushed to master.

Uros.

diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c
index 931b3362144..4185f58eed5 100644
--- a/gcc/config/i386/i386-expand.c
+++ b/gcc/config/i386/i386-expand.c
@@ -4124,8 +4124,8 @@ ix86_expand_int_sse_cmp (rtx dest, enum rtx_code code, 
rtx cop0, rtx cop1,
 
   /* XOP supports all of the comparisons on all 128-bit vector int types.  */
   if (TARGET_XOP
-      && (mode == V16QImode || mode == V8HImode
-         || mode == V4SImode || mode == V2DImode))
+      && GET_MODE_CLASS (mode) == MODE_VECTOR_INT
+      && GET_MODE_SIZE (mode) <= 16)
     ;
   /* AVX512F supports all of the comparsions
      on all 128/256/512-bit vector int types.  */
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 23d88a4c265..35e4123fa25 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -2121,6 +2121,62 @@ (define_insn "*gt<mode>3"
    (set_attr "type" "ssecmp")
    (set_attr "mode" "TI")])
 
+(define_insn "*xop_maskcmp<mode>3"
+  [(set (match_operand:MMXMODEI 0 "register_operand" "=x")
+       (match_operator:MMXMODEI 1 "ix86_comparison_int_operator"
+        [(match_operand:MMXMODEI 2 "register_operand" "x")
+         (match_operand:MMXMODEI 3 "register_operand" "x")]))]
+  "TARGET_XOP"
+  "vpcom%Y1<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
+  [(set_attr "type" "sse4arg")
+   (set_attr "prefix_data16" "0")
+   (set_attr "prefix_rep" "0")
+   (set_attr "prefix_extra" "2")
+   (set_attr "length_immediate" "1")
+   (set_attr "mode" "TI")])
+
+(define_insn "*xop_maskcmp<mode>3"
+  [(set (match_operand:VI_32 0 "register_operand" "=x")
+       (match_operator:VI_32 1 "ix86_comparison_int_operator"
+        [(match_operand:VI_32 2 "register_operand" "x")
+         (match_operand:VI_32 3 "register_operand" "x")]))]
+  "TARGET_XOP"
+  "vpcom%Y1<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
+  [(set_attr "type" "sse4arg")
+   (set_attr "prefix_data16" "0")
+   (set_attr "prefix_rep" "0")
+   (set_attr "prefix_extra" "2")
+   (set_attr "length_immediate" "1")
+   (set_attr "mode" "TI")])
+
+(define_insn "*xop_maskcmp_uns<mode>3"
+  [(set (match_operand:MMXMODEI 0 "register_operand" "=x")
+       (match_operator:MMXMODEI 1 "ix86_comparison_uns_operator"
+        [(match_operand:MMXMODEI 2 "register_operand" "x")
+         (match_operand:MMXMODEI 3 "register_operand" "x")]))]
+  "TARGET_XOP"
+  "vpcom%Y1u<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
+  [(set_attr "type" "ssecmp")
+   (set_attr "prefix_data16" "0")
+   (set_attr "prefix_rep" "0")
+   (set_attr "prefix_extra" "2")
+   (set_attr "length_immediate" "1")
+   (set_attr "mode" "TI")])
+
+(define_insn "*xop_maskcmp_uns<mode>3"
+  [(set (match_operand:VI_32 0 "register_operand" "=x")
+       (match_operator:VI_32 1 "ix86_comparison_uns_operator"
+        [(match_operand:VI_32 2 "register_operand" "x")
+         (match_operand:VI_32 3 "register_operand" "x")]))]
+  "TARGET_XOP"
+  "vpcom%Y1u<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
+  [(set_attr "type" "ssecmp")
+   (set_attr "prefix_data16" "0")
+   (set_attr "prefix_rep" "0")
+   (set_attr "prefix_extra" "2")
+   (set_attr "length_immediate" "1")
+   (set_attr "mode" "TI")])
+
 (define_expand "vec_cmp<mode><mode>"
   [(set (match_operand:MMXMODEI 0 "register_operand")
        (match_operator:MMXMODEI 1 ""