Christophe Lyon <christophe.l...@linaro.org> writes:
> In the meantime, I tried to make some progress, and looked at how
> things work on aarch64.
>
> This led me to define (in mve.md):
>
> (define_insn "@mve_vec_pack_trunc_lo_<mode>"
>  [(set (match_operand:<V_narrow> 0 "register_operand" "=w")
>        (truncate:<V_narrow> (match_operand:MVE_5 1 "register_operand" "w")))]
>  "TARGET_HAVE_MVE"
>  "vmovnb.i<V_sz_elem>   %q0, %q1\;"
>   [(set_attr "type" "mve_move")]
> )
>
> (define_insn "@mve_vec_pack_trunc_hi_<mode>"
>  [(set (match_operand:<V_narrow_pack> 0 "register_operand" "=w")
>        (vec_concat:<V_narrow_pack>
>                 (match_operand:<V_narrow> 1 "register_operand" "0")
>                 (truncate:<V_narrow>
>                         (match_operand:MVE_5 2 "register_operand" "w"))))]
>  "TARGET_HAVE_MVE"
>  "vmovnt.i<V_sz_elem>   %q0, %q2\;"
>   [(set_attr "type" "mve_move")]
> )
>
> and in vec-common.md, for
> (define_expand "vec_pack_trunc_<mode>"
>  [(set (match_operand:<V_narrow_pack> 0 "register_operand")
>        (vec_concat:<V_narrow_pack>
>                 (truncate:<V_narrow>
>                         (match_operand:VN 1 "register_operand"))
>                 (truncate:<V_narrow>
>                         (match_operand:VN 2 "register_operand"))))]
>
> I expand this for MVE:
>       rtx tmpreg = gen_reg_rtx (<V_narrow>mode);
>       emit_insn (gen_mve_vec_pack_trunc_lo (<MODE>mode, tmpreg, operands[1]));
>       emit_insn (gen_mve_vec_pack_trunc_hi (<MODE>mode, operands[0],
> tmpreg, operands[2]));
>
> I am getting an error in reload:
> error: unable to generate reloads for:
> (insn 10 9 11 2 (set (reg:V4HI 122 [ vect__4.16 ])
>         (truncate:V4HI (reg:V4SI 118 [ vect__4.16 ])))
> "/gcc.target/arm/simd/mve-vec-pack.c":17:112 3609
> {mve_vec_pack_trunc_lo_v4si}
>      (expr_list:REG_DEAD (reg:V4SI 118 [ vect__4.16 ])
>         (nil)))
>
> The next insn is:
> (insn 11 10 12 2 (set (reg:V8HI 121 [ vect__7.18 ])
>         (vec_concat:V8HI (reg:V4HI 122 [ vect__4.16 ])
>             (truncate:V4HI (reg:V4SI 119 [ vect__4.17 ]))))
> "/gcc.target/arm/simd/mve-vec-pack.c":17:112 3611
> {mve_vec_pack_trunc_hi_v4si}
>      (expr_list:REG_DEAD (reg:V4HI 122 [ vect__4.16 ])
>         (expr_list:REG_DEAD (reg:V4SI 119 [ vect__4.17 ])
>             (nil))))
>
> What is causing the reload error?

For this to work on MVE, we'd need to allow the 64-bit V_narrow modes to be
stored in MVE registers.  I'm not sure off-hand whether allowing that
would be a good idea or not.

If we continue to allow only 128-bit vectors in MVE registers then
we'll need to continue to use unspecs instead of truncate and vec_concat.

Thanks,
Richard

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