diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c
index ac4232f..70b7eb7 100644
--- a/gcc/common/config/i386/i386-common.c
+++ b/gcc/common/config/i386/i386-common.c
@@ -54,6 +54,7 @@ along with GCC; see the file COPYING3.  If not see
   (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
 #define OPTION_MASK_ISA_AVX2_SET \
   (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET)
+#define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
 
 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
    as -msse4.2.  */
@@ -121,6 +122,7 @@ along with GCC; see the file COPYING3.  If not see
    | OPTION_MASK_ISA_AVX2_UNSET)
 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
 #define OPTION_MASK_ISA_AVX2_UNSET OPTION_MASK_ISA_AVX2
+#define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
 
 /* SSE4 includes both SSE4.1 and SSE4.2.  -mno-sse4 should the same
    as -mno-sse4.1. */
@@ -309,6 +311,19 @@ ix86_handle_option (struct gcc_options *opts,
 	}
       return true;
 
+    case OPT_mrtm:
+      if (value)
+	{
+	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM_SET;
+	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_SET;
+	}
+      else
+	{
+	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RTM_UNSET;
+	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_UNSET;
+	}
+      return true;
+
     case OPT_msse4:
       opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
       opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
diff --git a/gcc/config.gcc b/gcc/config.gcc
index bdd5eb3..5060d900 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -349,7 +349,8 @@ i[34567]86-*-*)
 		       immintrin.h x86intrin.h avxintrin.h xopintrin.h
 		       ia32intrin.h cross-stdarg.h lwpintrin.h popcntintrin.h
 		       lzcntintrin.h bmiintrin.h bmi2intrin.h tbmintrin.h
-		       avx2intrin.h fmaintrin.h f16cintrin.h"
+		       avx2intrin.h fmaintrin.h f16cintrin.h rtmintrin.h
+		       xtestintrin.h"
 	;;
 x86_64-*-*)
 	cpu_type=i386
@@ -362,7 +363,8 @@ x86_64-*-*)
 		       immintrin.h x86intrin.h avxintrin.h xopintrin.h
 		       ia32intrin.h cross-stdarg.h lwpintrin.h popcntintrin.h
 		       lzcntintrin.h bmiintrin.h tbmintrin.h bmi2intrin.h
-		       avx2intrin.h fmaintrin.h f16cintrin.h"
+		       avx2intrin.h fmaintrin.h f16cintrin.h rtmintrin.h
+		       xtestintrin.h"
 	need_64bit_hwint=yes
 	;;
 ia64-*-*)
diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h
index 5da8fd2..6696b7a 100644
--- a/gcc/config/i386/cpuid.h
+++ b/gcc/config/i386/cpuid.h
@@ -68,6 +68,7 @@
 #define bit_BMI		(1 << 3)
 #define bit_AVX2	(1 << 5)
 #define bit_BMI2	(1 << 8)
+#define bit_RTM		(1 << 11)
 
 #if defined(__i386__) && defined(__PIC__)
 /* %ebx may be the PIC register.  */
diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i386-builtin-types.def
index d00b053..59d95ec 100644
--- a/gcc/config/i386/i386-builtin-types.def
+++ b/gcc/config/i386/i386-builtin-types.def
@@ -146,6 +146,8 @@ DEF_FUNCTION_TYPE (PVOID)
 
 DEF_FUNCTION_TYPE (FLOAT, FLOAT)
 DEF_FUNCTION_TYPE (FLOAT128, FLOAT128)
+DEF_FUNCTION_TYPE (CHAR, VOID)
+DEF_FUNCTION_TYPE (INT, VOID)
 DEF_FUNCTION_TYPE (INT, INT)
 DEF_FUNCTION_TYPE (INT, V16QI)
 DEF_FUNCTION_TYPE (INT, V2DF)
diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c
index d4b0b08..8adb3b4 100644
--- a/gcc/config/i386/i386-c.c
+++ b/gcc/config/i386/i386-c.c
@@ -261,6 +261,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
     def_or_undef (parse_in, "__AVX2__");
   if (isa_flag & OPTION_MASK_ISA_FMA)
     def_or_undef (parse_in, "__FMA__");
+  if (isa_flag & OPTION_MASK_ISA_RTM)
+    def_or_undef (parse_in, "__RTM__");
   if (isa_flag & OPTION_MASK_ISA_SSE4A)
     def_or_undef (parse_in, "__SSE4A__");
   if (isa_flag & OPTION_MASK_ISA_FMA4)
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index fad5e66..9eaf803 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -2682,6 +2682,7 @@ ix86_target_string (HOST_WIDE_INT isa, int flags, const char *arch,
     { "-mfsgsbase",	OPTION_MASK_ISA_FSGSBASE },
     { "-mrdrnd",	OPTION_MASK_ISA_RDRND },
     { "-mf16c",		OPTION_MASK_ISA_F16C },
+    { "-mrtm",		OPTION_MASK_ISA_RTM },
   };
 
   /* Flag options.  */
@@ -2930,6 +2931,7 @@ ix86_option_override_internal (bool main_args_p)
 #define PTA_XOP		 	(HOST_WIDE_INT_1 << 29)
 #define PTA_AVX2		(HOST_WIDE_INT_1 << 30)
 #define PTA_BMI2	 	(HOST_WIDE_INT_1 << 31)
+#define PTA_RTM		 	(HOST_WIDE_INT_1 << 32)
 /* if this reaches 64, need to widen struct pta flags below */
 
   static struct pta
@@ -2988,7 +2990,7 @@ ix86_option_override_internal (bool main_args_p)
 	| PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_AVX2
 	| PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE
 	| PTA_RDRND | PTA_F16C | PTA_BMI | PTA_BMI2 | PTA_LZCNT
-        | PTA_FMA | PTA_MOVBE},
+        | PTA_FMA | PTA_MOVBE | PTA_RTM},
       {"atom", PROCESSOR_ATOM, CPU_ATOM,
 	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 	| PTA_SSSE3 | PTA_CX16 | PTA_MOVBE},
@@ -3355,6 +3357,9 @@ ix86_option_override_internal (bool main_args_p)
 	if (processor_alias_table[i].flags & PTA_F16C
 	    && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_F16C))
 	  ix86_isa_flags |= OPTION_MASK_ISA_F16C;
+	if (processor_alias_table[i].flags & PTA_RTM
+	    && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_RTM))
+	  ix86_isa_flags |= OPTION_MASK_ISA_RTM;
 	if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
 	  x86_prefetch_sse = true;
 
@@ -4155,6 +4160,7 @@ ix86_valid_target_attribute_inner_p (tree args, char *p_strings[],
     IX86_ATTR_ISA ("fsgsbase",	OPT_mfsgsbase),
     IX86_ATTR_ISA ("rdrnd",	OPT_mrdrnd),
     IX86_ATTR_ISA ("f16c",	OPT_mf16c),
+    IX86_ATTR_ISA ("rtm",	OPT_mrtm),
 
     /* enum options */
     IX86_ATTR_ENUM ("fpmath=",	OPT_mfpmath_),
@@ -25547,6 +25553,12 @@ enum ix86_builtins
 
   IX86_BUILTIN_CLZS,
 
+  /* RTM */
+  IX86_BUILTIN_XBEGIN,
+  IX86_BUILTIN_XEND,
+  IX86_BUILTIN_XABORT,
+  IX86_BUILTIN_XTEST,
+
   /* BMI instructions.  */
   IX86_BUILTIN_BEXTR32,
   IX86_BUILTIN_BEXTR64,
@@ -25885,6 +25897,11 @@ static const struct builtin_description bdesc_special_args[] =
   { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
   { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
   { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
+
+  /* RTM */
+  { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) INT_FTYPE_VOID },
+  { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
+  { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) CHAR_FTYPE_VOID },
 };
 
 /* Builtins with variable number of arguments.  */
@@ -27331,6 +27348,10 @@ ix86_init_mmx_sse_builtins (void)
 	       V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
 	       IX86_BUILTIN_GATHERALTDIV8SI);
 
+  /* RTM.  */
+  def_builtin (OPTION_MASK_ISA_RTM, "__builtin_ia32_xabort",
+	       VOID_FTYPE_UNSIGNED, IX86_BUILTIN_XABORT);
+
   /* MMX access to the vec_init patterns.  */
   def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si",
 		     V2SI_FTYPE_INT_INT, IX86_BUILTIN_VEC_INIT_V2SI);
@@ -28770,6 +28791,8 @@ ix86_expand_special_args_builtin (const struct builtin_description *d,
       klass = store;
       memory = 0;
       break;
+    case CHAR_FTYPE_VOID:
+    case INT_FTYPE_VOID:
     case UINT64_FTYPE_VOID:
     case UNSIGNED_FTYPE_VOID:
       nargs = 0;
@@ -29567,6 +29590,19 @@ rdrand_step:
 
       return target;
 
+    case IX86_BUILTIN_XABORT:
+      icode = CODE_FOR_xabort;
+      arg0 = CALL_EXPR_ARG (exp, 0);
+      op0 = expand_normal (arg0);
+      mode0 = insn_data[icode].operand[0].mode;
+      if (!insn_data[icode].operand[0].predicate (op0, mode0))
+	{
+	  error ("the xabort's argument must be an 8-bit immediate");
+	  return const0_rtx;
+	}
+      emit_insn (gen_xabort (op0));
+      return 0;
+
     default:
       break;
     }
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 7721c46..c77070b 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -75,6 +75,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 #define TARGET_FSGSBASE	OPTION_ISA_FSGSBASE
 #define TARGET_RDRND	OPTION_ISA_RDRND
 #define TARGET_F16C	OPTION_ISA_F16C
+#define TARGET_RTM      OPTION_ISA_RTM
 
 #define TARGET_LP64	(TARGET_64BIT && !TARGET_X32)
 
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 6e2c123..7db680b 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -201,6 +201,12 @@
   UNSPECV_RDGSBASE
   UNSPECV_WRFSBASE
   UNSPECV_WRGSBASE
+
+  ;; For RTM support
+  UNSPECV_XBEGIN
+  UNSPECV_XEND
+  UNSPECV_XABORT
+  UNSPECV_XTEST
 ])
 
 ;; Constants to represent rounding modes in the ROUND instruction
@@ -18137,6 +18143,72 @@
   [(set_attr "length" "2")
    (set_attr "memory" "unknown")])
 
+(define_expand "xbegin"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(unspec_volatile:SI [(const_int 0)] UNSPECV_XBEGIN))
+   (set (match_dup 1)
+	(unspec_volatile:BLK [(match_dup 1)] UNSPECV_XBEGIN))]
+  "TARGET_RTM"
+{
+  operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
+  MEM_VOLATILE_P (operands[1]) = 1;
+  emit_move_insn (operands[0], constm1_rtx);
+  emit_insn (gen_xbegin_1 (operands[0], operands[1]));
+  DONE;
+})
+
+(define_insn "xbegin_1"
+  [(set (match_operand:SI 0 "register_operand" "=a")
+	(unspec_volatile:SI [(match_dup 0)] UNSPECV_XBEGIN))
+   (set (match_operand:BLK 1 "" "")
+	(unspec_volatile:BLK [(match_dup 1)] UNSPECV_XBEGIN))]
+  "TARGET_RTM"
+  "xbegin\t.+6"
+  [(set_attr "type" "other")
+   (set_attr "length" "3")])
+
+(define_insn "xend"
+  [(unspec_volatile [(const_int 0)] UNSPECV_XEND)]
+  "TARGET_RTM"
+  "xend"
+  [(set_attr "type" "other")
+   (set_attr "length" "3")])
+
+(define_insn "xabort"
+  [(unspec_volatile [(match_operand:SI 0 "const_0_to_255_operand" "n")]
+		    UNSPECV_XABORT)]
+  "TARGET_RTM"
+  "xabort\t%0"
+  [(set_attr "type" "other")
+   (set_attr "length" "3")])
+
+(define_expand "xtest"
+  [(set (match_operand:QI 0 "register_operand" "")
+	(unspec_volatile:QI [(const_int 0)] UNSPECV_XTEST))]
+  "TARGET_RTM"
+{
+  rtx insn, op0, op1;
+  op0 = gen_reg_rtx (QImode);
+  emit_move_insn (op0, const0_rtx);
+  op1 = gen_reg_rtx (QImode);
+  emit_move_insn (op1, const1_rtx);
+  emit_insn (gen_xtest_1 ());
+  insn = gen_rtx_EQ (VOIDmode, gen_rtx_REG (CCZmode, FLAGS_REG),
+		     const0_rtx);
+  emit_insn (gen_rtx_SET (VOIDmode, operands[0],
+			  gen_rtx_IF_THEN_ELSE (QImode, insn,
+						op1, op0)));
+  DONE;
+})
+
+(define_insn "xtest_1"
+  [(set (reg:CCZ FLAGS_REG)
+	(unspec_volatile:CCZ [(const_int 0)] UNSPECV_XTEST))]
+  "TARGET_RTM"
+  "xtest"
+  [(set_attr "type" "other")
+   (set_attr "length" "3")])
+
 (include "mmx.md")
 (include "sse.md")
 (include "sync.md")
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index 6c516e7..1d8dc44 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -573,3 +573,7 @@ Split 32-byte AVX unaligned load
 mavx256-split-unaligned-store
 Target Report Mask(AVX256_SPLIT_UNALIGNED_STORE) Save
 Split 32-byte AVX unaligned store
+
+mrtm
+Target Report Mask(ISA_RTM) Var(ix86_isa_flags) Save
+Support RTM built-in functions and code generation
diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h
index 986a573d..a477f05 100644
--- a/gcc/config/i386/immintrin.h
+++ b/gcc/config/i386/immintrin.h
@@ -80,6 +80,14 @@
 #include <f16cintrin.h>
 #endif
 
+#ifdef __RTM__
+#include <rtmintrin.h>
+#endif
+
+#ifdef __RTM__
+#include <xtestintrin.h>
+#endif
+
 #ifdef __RDRND__
 extern __inline int
 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
diff --git a/gcc/config/i386/rtmintrin.h b/gcc/config/i386/rtmintrin.h
new file mode 100644
index 0000000..f9f060f
--- /dev/null
+++ b/gcc/config/i386/rtmintrin.h
@@ -0,0 +1,77 @@
+/* Copyright (C) 2011 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#ifndef _IMMINTRIN_H_INCLUDED
+# error "Never use <rtmintrin.h> directly; include <immintrin.h> instead."
+#endif
+
+#ifndef __RTM__
+# error "RTM instruction set not enabled"
+#endif /* __RTM__ */
+
+#ifndef _RTMINTRIN_H_INCLUDED
+#define _RTMINTRIN_H_INCLUDED
+
+#define _XBEGIN_STARTED		(~0u)
+#define _XABORT_EXPLICIT	(1 << 0)
+#define _XABORT_RETRY		(1 << 1)
+#define _XABORT_CONFLICT	(1 << 2)
+#define _XABORT_CAPACITY	(1 << 3)
+#define _XABORT_DEBUG		(1 << 4)
+#define _XABORT_NESTED		(1 << 5)
+#define _XABORT_CODE(x)		(((x) >> 24) & 0xFF)
+
+/* Start an RTM code region.  Return _XBEGIN_STARTED on success and the
+   abort condition otherwise.  */
+extern __inline unsigned int
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_xbegin (void)
+{
+  return __builtin_ia32_xbegin ();
+}
+
+/* Specify the end of an RTM code region.  If it corresponds to the
+   outermost transaction, then attempts the transaction commit.  If the
+   commit fails, then control is transferred to the outermost transaction
+   fallback handler.  */
+extern __inline void
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_xend (void)
+{
+  __builtin_ia32_xend ();
+}
+
+/* Force an RTM abort condition. The control is transferred to the
+   outermost transaction fallback handler with the abort condition IMM.  */
+#ifdef __OPTIMIZE__
+extern __inline void
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_xabort (const unsigned int imm)
+{
+  __builtin_ia32_xabort (imm);
+}
+#else
+#define _xabort(N)  __builtin_ia32_xabort (N);
+#endif /* __OPTIMIZE__ */
+
+#endif /* _RTMINTRIN_H_INCLUDED */
diff --git a/gcc/config/i386/xtestintrin.h b/gcc/config/i386/xtestintrin.h
new file mode 100644
index 0000000..b3b92b2
--- /dev/null
+++ b/gcc/config/i386/xtestintrin.h
@@ -0,0 +1,44 @@
+/* Copyright (C) 2011 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#ifndef _IMMINTRIN_H_INCLUDED
+# error "Never use <xtestintrin.h> directly; include <immintrin.h> instead."
+#endif
+
+#ifndef __RTM__
+# error "RTM instruction set not enabled"
+#endif /* __RTM__ */
+
+#ifndef _XTESTINTRIN_H_INCLUDED
+#define _XTESTINTRIN_H_INCLUDED
+
+/* Return non-zero if the instruction executes inside an RTM or HLE code
+   region.  Return zero otherwise.   */
+extern __inline unsigned char
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_xtest (void)
+{
+  return __builtin_ia32_xtest ();
+}
+
+#endif /* _XTESTINTRIN_H_INCLUDED */
diff --git a/gcc/testsuite/gcc.target/i386/rtm-xabort-1.c b/gcc/testsuite/gcc.target/i386/rtm-xabort-1.c
new file mode 100644
index 0000000..7f12ad3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/rtm-xabort-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-mrtm -O0" } */
+/* { dg-final { scan-assembler "\txabort" } } */
+
+#include <immintrin.h>
+
+void
+rtm_test (void)
+{
+  _xabort (13);
+}
diff --git a/gcc/testsuite/gcc.target/i386/rtm-xbegin-1.c b/gcc/testsuite/gcc.target/i386/rtm-xbegin-1.c
new file mode 100644
index 0000000..adb6670
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/rtm-xbegin-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-mrtm -O0" } */
+/* { dg-final { scan-assembler "\txbegin" } } */
+
+#include <immintrin.h>
+
+unsigned int
+rtm_test (void)
+{
+  return _xbegin ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/rtm-xend-1.c b/gcc/testsuite/gcc.target/i386/rtm-xend-1.c
new file mode 100644
index 0000000..e79fead
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/rtm-xend-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-mrtm -O0" } */
+/* { dg-final { scan-assembler "\txend" } } */
+
+#include <immintrin.h>
+
+void
+rtm_test (void)
+{
+  _xend ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/rtm-xtest-1.c b/gcc/testsuite/gcc.target/i386/rtm-xtest-1.c
new file mode 100644
index 0000000..dc12bfc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/rtm-xtest-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-mrtm -O0 -dp" } */
+/* { dg-final { scan-assembler "\txtest" } } */
+
+#include <immintrin.h>
+
+int
+rtm_xtest (void)
+{
+  return _xtest ();
+}