On Fri, Feb 24, 2012 at 5:58 AM, H.J. Lu <hongjiu...@intel.com> wrote:
> The second form is redundant in
>
> ;; Stores and loads of ax to arbitrary constant address.
> ;; We fake an second form of instruction to force reload to load address
> ;; into register when rax is not available
> (define_insn "*movabs<mode>_1"
> [(set (mem:SWI1248x (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
> (match_operand:SWI1248x 1 "nonmemory_operand" "a,er"))]
> "TARGET_64BIT && ix86_check_movabs (insn, 0)"
> "@
> movabs{<imodesuffix>}\t{%1, %P0|%P0, %1}
> mov{<imodesuffix>}\t{%1, %a0|%a0, %1}"
> [(set_attr "type" "imov")
> (set_attr "modrm" "0,*")
> (set_attr "length_address" "8,0")
> (set_attr "length_immediate" "0,*")
> (set_attr "memory" "store")
> (set_attr "mode" "<MODE>")])
>
> since it is just normal mov<mode>. Tested on Linux/x86-64. OK for stage1?
I am a bit scarred by ... well ... scary comment that mentions reload.
This second form predates IRA - are we sure that IRA is clever enough
not to break due to this change?
Jan, Vladimir, do you have any comments?
Uros.
