Avoid emitting a strict low part move if the insv target actually affects the whole target reg.
Bootstrapped and regression tested on s390x. gcc/ChangeLog: PR target/102222 * config/s390/s390.c (s390_expand_insv): Emit a normal move if it is actually a full copy of the source operand into the target. Don't emit a strict low part move if source and target mode match. gcc/testsuite/ChangeLog: * gcc.target/s390/pr102222.c: New test. --- gcc/config/s390/s390.c | 10 ++++++++++ gcc/testsuite/gcc.target/s390/pr102222.c | 16 ++++++++++++++++ 2 files changed, 26 insertions(+) create mode 100644 gcc/testsuite/gcc.target/s390/pr102222.c diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index 54dd6332c3a..e04385451cf 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -6414,6 +6414,15 @@ s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src) if (bitsize + bitpos > GET_MODE_BITSIZE (mode)) return false; + /* Just a move. */ + if (bitpos == 0 + && bitsize == GET_MODE_BITSIZE (GET_MODE (src)) + && mode == GET_MODE (src)) + { + emit_move_insn (dest, src); + return true; + } + /* Generate INSERT IMMEDIATE (IILL et al). */ /* (set (ze (reg)) (const_int)). */ if (TARGET_ZARCH @@ -6510,6 +6519,7 @@ s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src) && (bitpos & 32) == ((bitpos + bitsize - 1) & 32) && MEM_P (src) && (mode == DImode || mode == SImode) + && mode != smode && register_operand (dest, mode)) { /* Emit a strict_low_part pattern if possible. */ diff --git a/gcc/testsuite/gcc.target/s390/pr102222.c b/gcc/testsuite/gcc.target/s390/pr102222.c new file mode 100644 index 00000000000..47d075e47fc --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/pr102222.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -m31 -mesa" } */ + +struct squashfs_reg_inode_header_1 read_inode_inode; + +int read_inode_val; + +struct squashfs_reg_inode_header_1 +{ + int file_size:32; +} __attribute__((packed)) read_inode (); + +void foo (void) +{ + read_inode_inode.file_size = read_inode_val; +} -- 2.31.1