On Mon, Jan 10, 2022 at 2:23 PM Haochen Jiang via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> Hi all,
>
> This patch removes the register restriction on operands for andnot insn so
> that it can be used from memory.
>
> Regtested on x86_64-pc-linux-gnu. Ok for trunk?
>
> BRs,
> Haochen
>
> gcc/ChangeLog:
>
> PR target/53652
> * config/i386/sse.md (*andnot<mode>3): Remove register restriction.
It should be "Extend predicate of operands[1] from register_operand to
vector_operand".
Similar for you commit message.
>
> gcc/testsuite/ChangeLog:
>
> PR target/53652
> * gcc.target/i386/pr53652-1.c: New test.
> ---
> gcc/config/i386/sse.md | 2 +-
> gcc/testsuite/gcc.target/i386/pr53652-1.c | 16 ++++++++++++++++
> 2 files changed, 17 insertions(+), 1 deletion(-)
> create mode 100644 gcc/testsuite/gcc.target/i386/pr53652-1.c
>
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index 0997d9edf9d..4448b875d35 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -16630,7 +16630,7 @@
> (define_insn "*andnot<mode>3"
> [(set (match_operand:VI 0 "register_operand" "=x,x,v")
> (and:VI
> - (not:VI (match_operand:VI 1 "register_operand" "0,x,v"))
> + (not:VI (match_operand:VI 1 "vector_operand" "0,x,v"))
> (match_operand:VI 2 "bcst_vector_operand" "xBm,xm,vmBr")))]
> "TARGET_SSE"
> {
> diff --git a/gcc/testsuite/gcc.target/i386/pr53652-1.c
> b/gcc/testsuite/gcc.target/i386/pr53652-1.c
> new file mode 100644
> index 00000000000..bd07ee29f4d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr53652-1.c
> @@ -0,0 +1,16 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -msse2" } */
> +/* { dg-final { scan-assembler-times "pandn\[ \\t\]" 2 } } */
> +/* { dg-final { scan-assembler-not "vpternlogq\[ \\t\]" } } */
> +
> +typedef unsigned long long vec __attribute__((vector_size (16)));
> +vec g;
> +vec f1 (vec a, vec b)
> +{
> + return ~a&b;
> +}
> +vec f2 (vec a, vec b)
> +{
> + return ~g&b;
> +}
> +
> --
> 2.18.1
>
--
BR,
Hongtao
